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full speed usb flash mcu family c8051f380/1/2/3/4/5/6/7 rev. 1.0 4/11 copyright ? 2011 by silicon laboratories c8051f380/1/2/3/4/5/6/7 analog peripherals - 10-bit adc (c8051f3 80/1/2/3 only) ? up to 500 ksps ? built-in analog multiplexer with single-ended and differential mode ? vref from external pin, internal reference, or v dd ? built-in temperature sensor ? external conversion start input option - two comparators - internal voltage reference (c8051f380/1/2/3 only) - brown-out detector and por circuitry usb function controller - usb specification 2.0 compliant - full speed (12 mbps) or low speed (1.5 mbps) operation - integrated clock recovery; no external crystal required for full speed or low speed - supports eight flexible endpoints - 1 kb usb buffer memory - integrated transceiver; no external resistors required on-chip debug - on-chip debug circuitry facilitates full speed, non-intru- sive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets voltage supply input: 2.7 to 5.25 v - voltages from 2.7 to 5.25 v supported using on-chip voltage regulators high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 48 mips operation - expanded interrupt handler memory - 4352 or 2304 bytes ram - 64 or 32 kb flash; in-system programmable in 512-byte sectors digital peripherals - 40/25 port i/o; all 5 v tolerant with high sink current - hardware enhanced spi?, two i 2 c/smbus?, and two enhanced uart serial ports - six general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with five cap- ture/compare modules - external memory interface (emif) clock sources - internal oscillator: 0.25% accuracy with clock recovery enabled. supports all usb and uart modes - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - low frequency (80 khz) internal oscillator - can switch between cl ock sources on-the-fly packages - 48-pin tqfp (c8051f380/2/4/6) - 32-pin lqfp (c8051f381/3/5/7) - 5x5 mm 32-pin qfn (c8051f381/3/5/7) temperature range: ?40 to +85 c analog peripherals 10-bit 500 ksps adc 64/32 kb isp flash 4/2 kb ram por debug circuitry flexible interrupts 8051 cpu 48 mips digital i/o precision internal oscillators high-speed controller core a m u x crossbar + - wdt + - usb controller / transceiver port 0 port 1 port 2 port 3 temp sensor vreg vref port 4 ext. memory i/f 48 pin only uart0 smbus0 pca 4 timers spi uart1 c8051f380/1/2/3 only smbus1
c8051f380/1/2/3/4/5/6/7 2 rev. 1.0
rev. 1.0 3 c8051f380/1/2/3/4/5/6/7 table of contents 1. system overview ........ ................ ................. ................ ................. ................ ........... 16 2. c8051f34x compatibility ........... ................. ................ ................. ................ ........... 20 2.1. hardware incompatibilities ... ................. ................ ................. ................ ........... 21 3. pinout and package definitions ..... ................ ................. .............. .............. ........... 22 4. electrical characteristics ......... ................ ................. ................ ................. ............. 34 4.1. absolute maximum specificat ions................ .............. .............. .............. ........... 34 4.2. electrical characteri stics ................ .............. .............. .............. .............. ........... 35 5. 10-bit adc (adc0, c 8051f380/1/2/3 only)........ .............. .............. .............. ........... 43 5.1. output code formatting ....... ................. ................ ................. ................ ........... 44 5.2. modes of operation ... ................ ................ ................. .............. .............. ........... 44 5.2.1. starting a conversion...... ................ ................ ................. .............. ........... 44 5.2.2. tracking modes............... ................ ................ ................. .............. ........... 46 5.2.3. settling time requirement s................. .............. .............. .............. ........... 47 5.3. programmable window detector ............... ................. .............. .............. ........... 51 5.3.1. window detector example. ............... ................. .............. .............. ........... 53 5.4. adc0 analog multiplexe r (c8051f380/1/2/3 only) ................. ................ ........... 54 6. voltage reference options ........ ................. ................ ................. ................ ........... 57 7. comparator0 and comparator1.... ................ ................ ................. .............. ........... 59 7.1. comparator multiple xers ............. ................. .............. .............. .............. ........... 66 8. voltage regulators (reg0 and re g1).............. .............. .............. .............. ........... 69 8.1. voltage regulator (r eg0)........... ................. .............. .............. .............. ........... 69 8.1.1. regulator mode selection. ................ ................. .............. .............. ........... 69 8.1.2. vbus detection .... ................. .............. .............. .............. .............. ........... 69 8.2. voltage regulator (r eg1)........... ................. .............. .............. .............. ........... 72 9. power management modes........ ................. ................ ................. ................ ........... 74 9.1. idle mode.............. ................ ................. ................ ................. ................ ........... 74 9.2. stop mode ................. ................ ................ ................. .............. .............. ........... 75 9.3. suspend mode .......... ................ ................ ................. .............. .............. ........... 75 10. cip-51 microcontroller.............. ................. ................ ................. ................ ........... 77 10.1. instruction set....... ................. ................ ................ ................. .............. ........... 78 10.1.1. instruction and cpu timi ng ...................... ................ ................. ............. 78 10.2. cip-51 register descriptions .. ................ ................. .............. .............. ........... 83 11. prefetch engine......... ................ ................. ................ ................. ................ ........... 86 12. memory organization .... ................ ................ ................. .............. .............. ........... 87 12.0.1. program memory ... .............. .............. .............. .............. .............. ........... 88 12.0.2. data memory....... ................. .............. .............. .............. .............. ........... 88 12.0.3. general purpose register s................ .............. .............. .............. ........... 89 12.0.4. bit addressable locations ............... ................. .............. .............. ........... 89 12.0.5. stack .......... ................ ................. ................ ................. ................ ........... 89 13. external data memory interface and on-c hip xram ......... ............ ........... ......... 90 13.1. accessing xram......... ................. .............. .............. .............. .............. ........... 90 13.1.1. 16-bit movx example ..... ............... ................. .............. .............. ........... 90 13.1.2. 8-bit movx exam ple ............... ................. ................ ................. ............. 90
c8051f380/1/2/3/4/5/6/7 4 rev. 1.0 13.2. accessing usb fifo space ... ................ ................. .............. .............. ........... 91 13.3. configuring the external me mory interface ....... ................ ................. ............. 92 13.4. port configuration.... ................ ................ ................. .............. .............. ........... 92 13.5. multiplexed and n on-multiplexed selection.............. .............. .............. ........... 95 13.5.1. multiplexed confi guration............ ................ ................. ................ ........... 95 13.5.2. non-multiplexed configuration............. .............. .............. .............. ......... 95 13.6. memory mode selection........ ................ ................ ................. .............. ........... 97 13.6.1. internal xram only ...... ................ ................ ................. .............. ........... 97 13.6.2. split mode without bank se lect.............. .............. ............... ........... ......... 97 13.6.3. split mode with bank sele ct............... .............. .............. .............. ........... 98 13.6.4. external only..... ................ ................. .............. .............. .............. ........... 98 13.7. timing .......... ................. .............. .............. .............. .............. .............. ........... 99 13.7.1. non-multiplexed mode .... ................ .............. ............... .............. ........... 101 13.7.1.1. 16-bit movx: emi0 cf[4:2] = 101, 110, or 111. ................. ........... 101 13.7.1.2. 8-bit movx withou t bank select: emi0cf[4:2] = 101 or 111 ....... 102 13.7.1.3. 8-bit movx with bank select: emi0cf[4:2] = 110 ............ ........... 103 13.7.2. multiplexed mode .............. .............. .............. ............... .............. ........... 104 13.7.2.1. 16-bit movx: emi0 cf[4:2] = 001, 010, or 011. ................. ........... 104 13.7.2.2. 8-bit movx withou t bank select: emi0cf[4:2] = 001 or 011 ....... 105 13.7.2.3. 8-bit movx with bank select: emi0cf[4:2] = 010 ............ ........... 106 14. special function registers...... ................. ................ ................. .............. ........... 108 14.1. 13.1. sfr paging .... ................ ................ .............. ............... .............. ........... 108 15. interrupts .......... ................ ................ .............. .............. ............... .............. ........... 115 15.1. mcu interrupt sour ces and vectors........... .............. .............. .............. ......... 116 15.1.1. interrupt priorities....... ................. ................ ................. .............. ........... 116 15.1.2. interrupt latency ........... ................ ................ ............... .............. ........... 116 15.2. interrupt register descripti ons ................ .............. ............... .............. ........... 116 15.3. int0 and int1 external interrupt sources ............ ............... .............. ........... 124 16. reset sources .................... .............. .............. .............. ............... .............. ........... 126 16.1. power-on reset ...... ................ ................ .............. ............... .............. ........... 127 16.2. power-fail reset / vdd moni tor .................... ................. ................ .............. 127 16.3. external reset ................ ................ ................ ................. ................ .............. 129 16.4. missing clock detector rese t ................. .............. ............... .............. ........... 129 16.5. comparator0 reset ............ ................. ................ ................. .............. ........... 129 16.6. pca watchdog timer reset ..... .............. .............. ............... .............. ........... 130 16.7. flash error reset .... ................ ................ .............. ............... .............. ........... 130 16.8. software reset ........ ................ ................ .............. ............... .............. ........... 130 16.9. usb reset............ ................. ................ ................ ............... .............. ........... 130 17. flash memory.............. ................. ................ ................ ............... .............. ........... 132 17.1. programming the flash memo ry ............... .............. .............. .............. ......... 132 17.1.1. flash lock and key functi ons ............... ................. ................ .............. 132 17.1.2. flash erase procedure ..... .............. .............. ............... .............. ........... 132 17.1.3. flash write procedure ..... ............... .............. ............... .............. ........... 133 17.2. non-volatile data storage.. ................. ................ ................. .............. ........... 134 17.3. security options ... ................. ................ ................ ............... .............. ........... 134
rev. 1.0 5 c8051f380/1/2/3/4/5/6/7 18. oscillators and clock selection ............ ................. ................ ................. ........... 139 18.1. system clock selection..... ............... ................. ................ ................. ........... 140 18.2. usb clock selection ............. ................ ................ ............... .............. ........... 140 18.3. programmable internal high-frequency (h-f) oscillator .. ................. ........... 142 18.3.1. internal oscillator su spend mode ............. ................ ................. ........... 142 18.4. clock multiplier ..... ................. ................ ................ ............... .............. ........... 144 18.5. programmable internal lo w-frequency (l-f) oscillator .. ............... .............. 145 18.5.1. calibrating the internal l-f oscillator..... ................. ................ .............. 145 18.6. external oscillator drive circuit........ ................. ................ ................. ........... 146 18.6.1. external crystal mode... ................ ................ ............... .............. ........... 146 18.6.2. external rc example.... ................ ................ ............... .............. ........... 148 18.6.3. external capacitor exam ple............... .............. .............. .............. ......... 148 19. port input/output ...... ................ ................. ................ ................. .............. ........... 150 19.1. priority crossbar decoder . ............... ................. ................ ................. ........... 151 19.2. port i/o initializatio n ................ ................ .............. ............... .............. ........... 155 19.3. general purpose port i/o ... ................. ................ ................. .............. ........... 158 20. universal serial bus controll er (usb0) .............. ................. ................ .............. 169 20.1. endpoint addressing ........ ................ ................. ................ ................. ........... 169 20.2. usb transceiver ..... ................ ................ .............. ............... .............. ........... 170 20.3. usb register access ......... ................. ................ ................. .............. ........... 172 20.4. usb clock configuration....... ................ ................ ............... .............. ........... 176 20.5. fifo management ...... .............. .............. .............. ............... .............. ........... 178 20.5.1. fifo split mode .. .............. .............. .............. ............... .............. ........... 178 20.5.2. fifo double buffering ... ................. .............. ............... .............. ........... 179 20.5.1. fifo access ....... .............. .............. .............. ............... .............. ........... 179 20.6. function addressing ................ ................ .............. ............... .............. ........... 180 20.7. function configur ation and control......... .............. ............... .............. ........... 180 20.8. interrupts ....... ................. ................ ................ ................. ................ .............. 183 20.9. the serial interface engine ................. ................ ................. .............. ........... 190 20.10. endpoint0 .............. ................ ................ .............. ............... .............. ........... 190 20.10.1. endpoint0 setup transa ctions ............... ................. .............. ........... 190 20.10.2. endpoint0 in transactions............... .............. .............. .............. ......... 190 20.10.3. endpoint0 out transacti ons............... ................. ................ .............. 191 20.11. configuring e ndpoints1-3 ........... .............. .............. .............. .............. ......... 193 20.12. controlling en dpoints1-3 in............... ................ ................. .............. ........... 194 20.12.1. endpoints1-3 in interr upt or bulk mode............. ............ ............ ......... 194 20.12.2. endpoints1-3 in isoc hronous mode.......... ................. .............. ........... 195 20.13. controlling endpoi nts1-3 out........ ................. ................ ................. ........... 198 20.13.1. endpoints1-3 out inte rrupt or bulk mode............ ................ .............. 198 20.13.2. endpoints1-3 out isochronous mode............. .............. ............ ......... 198 21. smbus0 and smbus1 (i2c compat ible)............ .............. .............. ............ ......... 202 21.1. supporting document s ................. .............. .............. .............. .............. ......... 203 21.2. smbus configuration.......... ................. ................ ................. .............. ........... 203 21.3. smbus operation ...... ................ .............. .............. ............... .............. ........... 203 21.3.1. transmitter vs. receiver ................. .............. ............... .............. ........... 204
c8051f380/1/2/3/4/5/6/7 6 rev. 1.0 21.3.2. arbitration........ ................ ................ .............. ............... .............. ........... 204 21.3.3. clock low extension..... ................ ................ ............... .............. ........... 204 21.3.4. scl low timeout .............. .............. .............. ............... .............. ........... 204 21.3.5. scl high (smbus free) timeout ............... ................. .............. ........... 205 21.4. using the smbus.............. ................ ................. ................ ................. ........... 205 21.4.1. smbus configuration regi ster............. .............. .............. ............ ......... 205 21.4.2. smbus timing control r egister................ ................ ................. ........... 207 21.4.3. smbncn control register .............. .............. ............... .............. ........... 211 21.4.3.1. software ack generat ion .................. ................. .............. ........... 211 21.4.3.2. hardware ack generat ion ............ ................. ................ .............. 211 21.4.4. hardware slave address recognition . .............. .............. ............ ......... 214 21.4.5. data register .... ................ .............. .............. ............... .............. ........... 218 21.5. smbus transfer modes......... ................ ................ ............... .............. ........... 220 21.5.1. write sequence (master) .. .............. .............. ............... .............. ........... 220 21.5.2. read sequence (master) .. .............. .............. ............... .............. ........... 221 21.5.3. write sequence (slave) ... ............... .............. ............... .............. ........... 222 21.5.4. read sequence (slave) .... .............. .............. ............... .............. ........... 223 21.6. smbus status decodi ng................... ................. ................ ................. ........... 223 22. uart0 ............... ................ ................ .............. .............. ............... .............. ........... 229 22.1. enhanced baud rate generati on............ .............. ............... .............. ........... 230 22.2. operational modes ........... ................ ................. ................ ................. ........... 231 22.2.1. 8-bit uart ........ ................ .............. .............. ............... .............. ........... 231 22.2.2. 9-bit uart ........ ................ .............. .............. ............... .............. ........... 232 22.3. multiprocessor communication s ................ .............. .............. .............. ......... 233 23. uart1 ............... ................ ................ .............. .............. ............... .............. ........... 237 23.1. baud rate generator ................ .............. .............. ............... .............. ........... 238 23.2. data format.......... ................. ................ ................ ............... .............. ........... 239 23.3. configuration and o peration ............ ................. ................ ................. ........... 240 23.3.1. data transmission ........ ................ ................ ............... .............. ........... 240 23.3.2. data reception ... .............. .............. .............. ............... .............. ........... 240 23.3.3. multiprocessor communic ations ............... ................ ................. ........... 241 24. enhanced serial peripheral interface (spi0) ...... ................. ................ .............. 247 24.1. signal descriptions........... ................ ................. ................ ................. ........... 248 24.1.1. master out, slave in (mosi)........... .............. ............... .............. ........... 248 24.1.2. master in, slave out (m iso).............. .............. .............. .............. ......... 248 24.1.3. serial clock (sck ) ................. ................ ................. ................ .............. 248 24.1.4. slave select (nss) .............. .............. .............. .............. .............. ......... 248 24.2. spi0 master mode op eration .................. .............. ............... .............. ........... 248 24.3. spi0 slave m ode operation ................ ................ ................. .............. ........... 250 24.4. spi0 interrupt sources ..... ................ ................. ................ ................. ........... 250 24.5. serial clock phase and pola rity .............. .............. ............... .............. ........... 251 24.6. spi special function regist ers ............... .............. ............... .............. ........... 253 25. timers ................... ................. ................ ................ ................. ................ .............. 26 0 25.1. timer 0 and timer 1 ... ............... .............. .............. ............... .............. ........... 263 25.1.1. mode 0: 13-bit counte r/timer ......... .............. ............... .............. ........... 263
rev. 1.0 7 c8051f380/1/2/3/4/5/6/7 25.1.2. mode 1: 16-bit counte r/timer ......... .............. ............... .............. ........... 264 25.1.3. mode 2: 8-bit counte r/timer with auto-reload....... ................ .............. 264 25.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ............... .............. 265 25.2. timer 2 .......... ................. ................ ................ ................. ................ .............. 271 25.2.1. 16-bit timer with auto-r eload.............. .............. .............. ............ ......... 271 25.2.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 272 25.2.3. timer 2 capture m odes: usb start-of-frame or lfo falling edge ..... 272 25.3. timer 3 .......... ................. ................ ................ ................. ................ .............. 278 25.3.1. 16-bit timer with auto-r eload.............. .............. .............. ............ ......... 278 25.3.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 279 25.3.3. timer 3 capture m odes: usb start-of-frame or lfo falling edge ..... 279 25.4. timer 4 .......... ................. ................ ................ ................. ................ .............. 285 25.4.1. 16-bit timer with auto-r eload.............. .............. .............. ............ ......... 285 25.4.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 286 25.5. timer 5 .......... ................. ................ ................ ................. ................ .............. 290 25.5.1. 16-bit timer with auto-r eload.............. .............. .............. ............ ......... 290 25.5.2. 8-bit timers with auto -reload............ .............. .............. .............. ......... 291 26. programmable counter array............ .............. .............. .............. .............. ......... 295 26.1. pca counter/timer ............ ................. ................ ................. .............. ........... 296 26.2. pca0 interrupt sources..... ............... ................. ................ ................. ........... 297 26.3. capture/compare modules ..... ................ .............. ............... .............. ........... 298 26.3.1. edge-triggered capture mode.............. .............. .............. ............ ......... 299 26.3.2. software timer (compar e) mode.............. ................ ................. ........... 300 26.3.3. high-speed output mode . .............. .............. ............... .............. ........... 301 26.3.4. frequency output mode .. ............... .............. ............... .............. ........... 302 26.3.5. 8-bit pulse width modu lator mode ........... ................ ................. ........... 303 26.3.6. 16-bit pulse width m odulator mode......... ................ ................. ........... 304 26.4. watchdog timer mode .............. .............. .............. ............... .............. ........... 305 26.4.1. watchdog timer o peration .................. .............. .............. ............ ......... 305 26.4.2. watchdog timer usage .... .............. .............. ............... .............. ........... 306 26.5. register descriptions for pc a0............... .............. ............... .............. ........... 308 27. c2 interface ............. ................ ................ ................. ................ ................. ........... 313 27.1. c2 interface registers...... ................ ................. ................ ................. ........... 313 27.2. c2 pin sharing ..... ................. ................ ................ ............... .............. ........... 316 contact information.......... ................. ................ ................ ............... .............. ........... 318
c8051f380/1/2/3/4/5/6/7 8 rev. 1.0 list of figures figure 1.1. c8051f380/2/4/6 block diagram .............. ................. ................ ........... 18 figure 1.2. c8051f381/3/5/7 block diagram .............. ................. ................ ........... 19 figure 3.1. tqfp-48 pinou t diagram (top view) .............. .............. .............. ......... 25 figure 3.2. tqfp-48 package diagram ............... .............. .............. .............. ......... 26 figure 3.3. tqfp-48 recommende d pcb land pattern ............. ................ ........... 27 figure 3.4. lqfp-32 pinou t diagram (top view) ............... .............. .............. ......... 28 figure 3.5. lqfp-32 package diagram ............... .............. .............. .............. ......... 29 figure 3.6. lqfp-32 recommende d pcb land pattern ............. ................ ........... 30 figure 3.7. qfn-32 pinout diagram (top view) ......... ................. ................ ........... 31 figure 3.8. qfn-32 package drawin g ...................... ................ ................. ............. 32 figure 3.9. qfn-32 recommended pcb land pattern ... .............. .............. ........... 33 figure 5.1. adc0 functional blo ck diagram ............. ................ ................. ............. 43 figure 5.2. 10-bit adc track and conversion exampl e timing ........... ............ ...... 46 figure 5.3. adc0 equival ent input circuits ........ .............. .............. .............. ........... 47 figure 5.4. adc window compare example: right-justified data ......... ................ 53 figure 5.5. adc window compare example: left-justified data ........... ................ 53 figure 6.1. voltage reference f unctional block diagram ....... ............ ........... ......... 57 figure 7.1. comparator0 functiona l block diagram ............... ............ ........... ......... 59 figure 7.2. comparator1 functiona l block diagram ............... ............ ........... ......... 60 figure 7.3. comparator hysteresis plot ................. .............. ............... ........... ......... 61 figure 7.4. comparator input mu ltiplexer block diagram ........ ............ ........... ......... 66 figure 8.1. reg0 configuration: usb bus-powered .. ................. ................ ........... 69 figure 8.2. reg0 configuration: usb self-powered .. ................. ................ ........... 70 figure 8.3. reg0 configuratio n: usb self-powered, regulator disabled .............. 70 figure 8.4. reg0 configuratio n: no usb connection ................. ................ ........... 71 figure 10.1. cip-51 block diagram .. ............... ................. .............. .............. ........... 77 figure 12.1. on-chip memory map for 64 kb devices (c8051f 380/1/4/5) .. ........... 87 figure 12.2. on-chip memory map for 32 kb devices (c8051f 382/3/6/7) .. ........... 88 figure 13.1. usb fifo space and xram me mory map with usbfae set to ?1? ... 91 figure 13.2. multiplexed configur ation example ......... ................. ................ ........... 95 figure 13.3. non-multiplexed conf iguration example ............. ............ ........... ......... 96 figure 13.4. emif operati ng modes .................. .............. .............. .............. ........... 97 figure 13.5. non-multiplexed 16- bit movx timing ..... ................. .............. ........... 101 figure 13.6. non-multiplexed 8- bit movx without bank sele ct timing ................ 102 figure 13.7. non-multiplexed 8- bit movx with bank select timing ....... .............. 103 figure 13.8. multiplexed 16-bit movx timing ........... ................ ................. ........... 104 figure 13.9. multiplexed 8-bit movx without bank select ti ming .......... .............. 105 figure 13.10. multiplexed 8-bit movx with bank select timi ng ............. .............. 106 figure 16.1. reset sources ........ ................. ................ ................. .............. ........... 126 figure 16.2. power-on and vdd monitor reset timing .............. .............. ........... 127 figure 17.1. flash program memo ry map and security byte .. ................ .............. 134 figure 18.1. oscillator options .. ............... ................. ................ ................. ........... 139 figure 18.2. external crystal exam ple ................... ................. ................ .............. 147
rev. 1.0 9 c8051f380/1/2/3/4/5/6/7 figure 19.1. port i/o functional block diagram (port 0 through port 3) ............... 150 figure 19.2. port i/o cell block diagram ........ .............. ............... .............. ........... 151 figure 19.3. peripheral availabili ty on port i/o pins ................ ................ .............. 152 figure 19.4. crossbar priority de coder in example configuration (no pins skipped) .............. ................ ................. ................ .............. 153 figure 19.5. crossbar priority de coder in example configuration (3 pins skipped) ............ .............. .............. ............... .............. ........... 154 figure 20.1. usb0 block diagram .. ................. .............. ............... .............. ........... 169 figure 20.2. usb0 register a ccess scheme ............ ................ ................. ........... 172 figure 20.3. usb fifo allocation .. ................. .............. ............... .............. ........... 178 figure 21.1. smbus block diagram ................ .............. ............... .............. ........... 202 figure 21.2. typical smbus confi guration ................ ................ ................. ........... 203 figure 21.3. smbus transaction ..... ................ .............. ............... .............. ........... 204 figure 21.4. typical smbus scl generation ............ ................ ................. ........... 206 figure 21.5. typical master wr ite sequence ............ ................ ................. ........... 220 figure 21.6. typical mast er read sequence ....... .............. .............. ............ ......... 221 figure 21.7. typical slave writ e sequence .............. ................ ................. ........... 222 figure 21.8. typical slave read sequence .............. ................ ................. ........... 223 figure 22.1. uart0 block diagram ............ ................ ................. .............. ........... 229 figure 22.2. uart0 baud rate logi c ................ .............. .............. .............. ......... 230 figure 22.3. uart interconnect di agram ................. ................ ................. ........... 231 figure 22.4. 8-bit uart timing diagram ........... .............. .............. .............. ......... 231 figure 22.5. 9-bit uart timing diagram ........... .............. .............. .............. ......... 232 figure 22.6. uart multi-proc essor mode interconnect diagr am ........... .............. 233 figure 23.1. uart1 block diagram ............ ................ ................. .............. ........... 237 figure 23.2. uart1 timing without parity or extra bit .... .............. .............. ......... 239 figure 23.3. uart1 timing with pa rity .......... .............. ............... .............. ........... 239 figure 23.4. uart1 timing with extra bit ............. ................. ................ .............. 239 figure 23.5. typical uart inte rconnect diagram ................ ............ ............ ......... 240 figure 23.6. uart multi-proc essor mode interconnect diagr am ........... .............. 241 figure 24.1. spi blo ck diagram ........... .............. .............. .............. .............. ......... 247 figure 24.2. multiple-master mo de connection diagram ........ ................ .............. 249 figure 24.3. 3-wi re single master and 3-wi re single slave mode connection diagram ............. ................. ................ ................. ........... 249 figure 24.4. 4-wi re single master mode and 4-wire slave mode connection diagram ........... ................ ................. ................ .............. 250 figure 24.5. master mode data/ clock timing ........... ................ ................. ........... 252 figure 24.6. slave mode data/clock timing (ckpha = 0) .............. ............ ......... 252 figure 24.7. slave mode data/clock timing (ckpha = 1) .............. ............ ......... 253 figure 24.8. spi mast er timing (ckpha = 0) . .............. ............... .............. ........... 257 figure 24.9. spi mast er timing (ckpha = 1) . .............. ............... .............. ........... 257 figure 24.10. spi slave timing (c kpha = 0) ........... ................ ................. ........... 258 figure 24.11. spi slave timing (c kpha = 1) ........... ................ ................. ........... 258 figure 25.1. t0 mode 0 block diagr am .............. .............. .............. .............. ......... 264 figure 25.2. t0 mode 2 block diagr am .............. .............. .............. .............. ......... 265
c8051f380/1/2/3/4/5/6/7 10 rev. 1.0 figure 25.3. t0 mode 3 block diagr am .............. .............. .............. .............. ......... 266 figure 25.4. timer 2 16-bit mode block diagram ..... ................ ................. ........... 271 figure 25.5. timer 2 8-bi t mode block diagram .. .............. .............. ............ ......... 272 figure 25.6. timer 2 capture mode (t2split = 0) ... ................ ................. ........... 273 figure 25.7. timer 2 capture mode (t2split = 0) ... ................ ................. ........... 274 figure 25.8. timer 3 16-bit mode block diagram ..... ................ ................. ........... 278 figure 25.9. timer 3 8-bi t mode block diagram .. .............. .............. ............ ......... 279 figure 25.10. timer 3 capture mode (t3split = 0) ............ ............ ............ ......... 280 figure 25.11. timer 3 capture mode (t3split = 0) ............ ............ ............ ......... 281 figure 25.12. timer 4 16- bit mode block diagram ............ .............. ............ ......... 285 figure 25.13. timer 4 8-bit mode block diagram ..... ................ ................. ........... 286 figure 25.14. timer 5 16- bit mode block diagram ............ .............. ............ ......... 290 figure 25.15. timer 5 8-bit mode block diagram ..... ................ ................. ........... 291 figure 26.1. pca block diagram ... ................ ................ ............... .............. ........... 295 figure 26.2. pca counter/timer block diagram ....... ................ ................. ........... 296 figure 26.3. pca interrupt block diagram ................ ................ ................. ........... 297 figure 26.4. pca capture mode dia gram ............ .............. .............. ............ ......... 299 figure 26.5. pca software time r mode diagram ....... ................. .............. ........... 300 figure 26.6. pca high-speed out put mode diagram ............. ................ .............. 301 figure 26.7. pca frequency output mode .......... .............. .............. ............ ......... 302 figure 26.8. pca 8-bit pwm mode diagram ......... ................. ................ .............. 303 figure 26.9. pca 16-bit pwm mode . .............. .............. ............... .............. ........... 304 figure 26.10. pca module 4 wi th watchdog timer enabled .... ................. ........... 305 figure 27.1. typical c2 pin shari ng ................ .............. ............... .............. ........... 316
rev. 1.0 11 c8051f380/1/2/3/4/5/6/7 list of tables table 1.1. product selection guide ............... ................ ................. .............. ........... 17 table 2.1. c8051f38x replacement part numbers ...... ................. .............. ........... 20 table 3.1. pin definitions for the c8051f380/1/2/3/4/5/6/7 ..... ............ ........... ......... 22 table 3.2. tqfp-48 package dimens ions ........... .............. .............. .............. ......... 26 table 3.3. tqfp-48 pcb land patt ern dimensions ................. ................. ............. 27 table 3.4. lqfp-32 package dimens ions ........... .............. .............. .............. ......... 29 table 3.5. lqfp-32 pcb land patt ern dimensions ................. ................. ............. 30 table 3.6. qfn-32 package dimensi ons ............. .............. .............. .............. ......... 32 table 3.7. qfn-32 pcb land pattern dimensions .............. ............... ........... ......... 33 table 4.1. absolute maximum ratings ............... .............. .............. .............. ........... 34 table 4.2. global electrical char acteristics ............ .............. ............... ........... ......... 35 table 4.3. port i/o dc elec trical characteristics .............. .............. .............. ........... 36 table 4.4. reset electrical characteristics ......... .............. .............. .............. ........... 36 table 4.5. internal voltage regula tor electrical characteristi cs ................ ............. 37 table 4.6. flash electrical charac teristics ......... .............. .............. .............. ........... 37 table 4.7. internal high-frequency oscillator electrical char acteristics .... ............. 38 table 4.8. internal low-frequen cy oscillator electrical char acteristics .... ............. 38 table 4.9. external oscillator el ectrical characteristics ....... ............... ........... ......... 38 table 4.10. adc0 electrical char acteristics ........... .............. ............... ........... ......... 39 table 4.11. temperature sensor electrical characteristics .... ............ ........... ......... 40 table 4.12. voltage reference electrical charac teristics ....... ............ ........... ......... 40 table 4.13. comparator electrical characteristics .... ................ ................. ............. 41 table 4.14. usb transceiver electrical characte ristics .......... ............ ........... ......... 42 table 10.1. cip-51 instruction set summary ............ ................ ................. ............. 79 table 13.1. ac parameters for external memory interface .. ............ ............ ......... 107 table 14.1. special function r egister (sfr) memory map .... ................ .............. 109 table 14.2. special function regi sters ........... .............. ............... .............. ........... 110 table 15.1. interrupt summary ... ................. ................ ................. .............. ........... 117 table 20.1. endpoint addressing scheme ................ ................ ................. ........... 170 table 20.2. usb0 controll er registers ........... .............. ............... .............. ........... 175 table 20.3. fifo configurations ................. ................ ................. .............. ........... 179 table 21.1. smbus clock source selection .............. ................ ................. ........... 206 table 21.2. minimum sda setup and hold times .... ................ ................. ........... 207 table 21.3. sources for hardwa re changes to smbncn ....... ................ .............. 214 table 21.4. hardware address recognition examples (ehack = 1) ................... 215 table 21.5. smbus status de coding: hardware ack disab led (ehack = 0) ...... 224 table 21.6. smbus status decoding: hardware ack e nabled (ehack = 1) ...... 226 table 22.1. timer settings for standard baud rates using the internal oscillator 236 table 23.1. baud rate genera tor settings for standard baud rates ................... 238 table 24.1. spi slave timing para meters ......... .............. .............. .............. ......... 259 table 26.1. pca timebase input op tions ............ .............. .............. ............ ......... 296 table 26.2. pca0cpm bit sett ings for pca capt ure/compare modules ............. 298 table 26.3. watchdog timer timeout intervals1 .. .............. .............. ............ ......... 307
c8051f380/1/2/3/4/5/6/7 12 rev. 1.0 list of registers sfr definition 5.1. adc0cf: adc0 configuration ........ ................ ................. ............. 48 sfr definition 5.2. adc0h: adc0 data word msb ...... ................ ................. ............. 49 sfr definition 5.3. adc0l: adc0 data word lsb ............... .............. .............. ........... 49 sfr definition 5.4. adc0cn : adc0 control ........... .............. .............. .............. ........... 50 sfr definition 5.5. adc0gth: adc0 greater-than da ta high byte ...... ........... ......... 51 sfr definition 5.6. adc0gtl: adc0 greater-than data low byte ............... ............. 51 sfr definition 5.7. adc0lth: adc0 less-than data high byte ............ ........... ......... 52 sfr definition 5.8. adc0ltl: ad c0 less-than data low byte .. ........... ........... ......... 52 sfr definition 5.9. amx0p: amux 0 positive channel select ..... ............ ........... ......... 55 sfr definition 5.10. amx0n: am ux0 negative channel select ... ................. ............. 56 sfr definition 6.1. ref0cn : reference control .... .............. .............. .............. ........... 58 sfr definition 7.1. cpt0cn: com parator0 control ....... ................ ................. ............. 62 sfr definition 7.2. cpt0md: com parator0 mode selection ....... ............ ........... ......... 63 sfr definition 7.3. cpt1cn: com parator1 control ....... ................ ................. ............. 64 sfr definition 7.4. cpt1md: com parator1 mode selection ....... ............ ........... ......... 65 sfr definition 7.5. cpt0mx: com parator0 mux selection ........ ............ ........... ......... 67 sfr definition 7.6. cpt1mx: com parator1 mux selection ........ ............ ........... ......... 68 sfr definition 8.1. reg 01cn: voltage regulator c ontrol ............ ................. ............. 73 sfr definition 9.1. pcon: power control ............ ................. .............. .............. ........... 76 sfr definition 10.1. dpl: data po inter low byte ....... .............. ............... ........... ......... 83 sfr definition 10.2. dph: data pointer high byte .. .............. .............. .............. ........... 83 sfr definition 10.3. sp: stack pointe r ................. ................. .............. .............. ........... 84 sfr definition 10.4. acc: accumulator ........ ................. ................ ................. ............. 84 sfr definition 10.5. b: b r egister ............. .............. .............. .............. .............. ........... 84 sfr definition 10.6. psw: program status word .......... ................ ................. ............. 85 sfr definition 11.1. pfe0cn: pref etch engine control .. ................. ................ ........... 86 sfr definition 13.1. emi0 cn: external memory interface co ntrol .............. ................ 93 sfr definition 13.2. emi0cf: exte rnal memory interface config uration ........ ............. 94 sfr definition 13.3. emi0tc: ex ternal memory timing control ........... ............ ......... 100 sfr definition 14.1. sfrpage: sf r page ................ ................. ................ .............. 108 sfr definition 15.1. ie: in terrupt enable .............. .............. ............... .............. ........... 118 sfr definition 15.2. ip: in terrupt priority .......... ................ ................. .............. ........... 119 sfr definition 15.3. eie1: exte nded interrupt enable 1 ........... ............ ............ ......... 120 sfr definition 15.4. eip1: extended interrupt priority 1 ........... ............ ............ ......... 121 sfr definition 15.5. eie2: exte nded interrupt enable 2 ........... ............ ............ ......... 122 sfr definition 15.6. eip2: extended interrupt priority 2 ........... ............ ............ ......... 123 sfr definition 15.7. it01cf: int0 /int1 configurationo .......... ............ ............ ......... 125 sfr definition 16.1. vdm0cn: vdd monitor control .... ................ ................. ........... 129 sfr definition 16.2. rstsrc: rese t source ............. ................. ................ .............. 131 sfr definition 17.1. psctl: prog ram store r/w contro l ............. ................. ........... 136 sfr definition 17.2. flkey: flas h lock and key .......... ................ ................. ........... 137 sfr definition 17.3. flscl: flash scale ............. .............. ............... .............. ........... 138 sfr definition 18.1. clksel: clock select ......... .............. ............... .............. ........... 141
rev. 1.0 13 c8051f380/1/2/3/4/5/6/7 sfr definition 18.2. oscicl: inte rnal h-f oscillator calibrati on ................ .............. 142 sfr definition 18.3. oscicn: inte rnal h-f oscillator control .. ............ ............ ......... 143 sfr definition 18.4. clkm ul: clock multiplier control ..... ............... .............. ........... 144 sfr definition 18.5. osclcn: inte rnal l-f oscillator control .. ............ ............ ......... 145 sfr definition 18.6. oscxcn: exte rnal oscillator control ....... ............ ............ ......... 149 sfr definition 19.1. xbr0: port i/o crossbar register 0 ....... .............. ............ ......... 156 sfr definition 19.2. xbr1: port i/o crossbar register 1 ....... .............. ............ ......... 157 sfr definition 19.3. xbr2: port i/o crossbar register 2 ....... .............. ............ ......... 158 sfr definition 19.4. p0: port 0 .... ................ ................ ................. ................ .............. 159 sfr definition 19.5. p0mdin: port 0 input mode ........ ................. ................ .............. 159 sfr definition 19.6. p0mdout: po rt 0 output mode .... ................ ................. ........... 160 sfr definition 19.7. p0skip: port 0 skip ........... ................ ............... .............. ........... 160 sfr definition 19.8. p1: port 1 .... ................ ................ ................. ................ .............. 161 sfr definition 19.9. p1mdin: port 1 input mode ........ ................. ................ .............. 161 sfr definition 19.10. p1mdout: po rt 1 output mode ............. ............ ............ ......... 162 sfr definition 19.11. p1skip: port 1 skip ........... .............. ............... .............. ........... 162 sfr definition 19.12. p2: port 2 .... ................ ................. ................ ................. ........... 163 sfr definition 19.13. p2mdin: port 2 input mode ...... ................. ................ .............. 163 sfr definition 19.14. p2mdout: po rt 2 output mode ............. ............ ............ ......... 164 sfr definition 19.15. p2skip: port 2 skip ........... .............. ............... .............. ........... 164 sfr definition 19.16. p3: port 3 .... ................ ................. ................ ................. ........... 165 sfr definition 19.17. p3mdin: port 3 input mode ...... ................. ................ .............. 165 sfr definition 19.18. p3mdout: po rt 3 output mode ............. ............ ............ ......... 166 sfr definition 19.19. p3skip: port 3 skip ........... .............. ............... .............. ........... 166 sfr definition 19.20. p4: port 4 .... ................ ................. ................ ................. ........... 167 sfr definition 19.21. p4mdin: port 4 input mode ...... ................. ................ .............. 167 sfr definition 19.22. p4mdout: po rt 4 output mode ............. ............ ............ ......... 168 sfr definition 20.1. usb0 xcn: usb0 transceiver control .. ............. .............. ......... 171 sfr definition 20.2. usb0 adr: usb0 indirect ad dress .......... ............ ............ ......... 173 sfr definition 20.3. usb0da t: usb0 data ........ .............. ............... .............. ........... 174 usb register definition 20.4. i ndex: usb0 endpoint index ................ ............ ......... 176 usb register definition 20.5. clkrec: clock recovery contro l ................ .............. 177 usb register definition 20.6. fifon: usb0 endpoint fifo a ccess ............ .............. 179 usb register definition 20.7. faddr: usb0 function address .. ............... .............. 180 usb register definition 20.8. power: usb0 powe r ............... ............ ............ ......... 182 usb register definition 20.9. framel: usb0 frame number low ........... .............. 183 usb register definition 20.10. frameh: usb0 frame number high ........ .............. 183 usb register definition 20.11. in1int: usb0 in endpoint inte rrupt ........... .............. 184 usb register definition 20.12. out1int: usb0 out endpoint interrupt ................. 185 usb register definition 20.13. cmint: usb0 common interrupt ............... .............. 186 usb register definition 20.14. in1ie: usb0 in endpoint inte rrupt enable . .............. 187 usb register definition 20.15. out1ie: u sb0 out endpoint inte rrupt enable ....... 188 usb register definition 20.16. cmie: usb0 common interrupt enable ...... .............. 189 usb register definition 20.17. e0csr: usb0 endpoint0 control ............... .............. 192 usb register definition 20.18. e0cnt: usb0 endpoint0 data count ......... .............. 193
c8051f380/1/2/3/4/5/6/7 14 rev. 1.0 usb register definition 20.19. eenable: usb0 endpoi nt enable ......... .................. 194 usb register definition 20.20. eincsrl: usb0 in endpoint control low ............... 196 usb register definition 20.21. eincsrh: usb0 in endpoint control high .............. 197 usb register definition 20. 22. eoutcsrl: usb0 out en dpoint control low byte 199 usb register definiti on 20.23. eoutcsrh: usb0 out endpoint control high byte ................ ................ ................ .............. .............. ............... .............. ........... 2 00 usb register definition 20.24. eoutcntl: usb0 out endp oint count low ......... 200 usb register definition 20. 25. eoutcnth: usb0 out en dpoint count high ........ 201 sfr definition 21.1. smb0cf: sm bus clock/configurat ion ................. ............ ......... 208 sfr definition 21.2. smb1cf: sm bus clock/configurat ion ................. ............ ......... 209 sfr definition 21.3. smbtc: smbu s timing control .... ................ ................. ........... 210 sfr definition 21.4. smb0cn: smbu s control .............. ................ ................. ........... 212 sfr definition 21.5. smb1cn: smbu s control .............. ................ ................. ........... 213 sfr definition 21.6. smb0adr: smbus0 slave address ......... ............ ............ ......... 215 sfr definition 21.7. smb0adm: smbus0 slave address mask ........... ............ ......... 216 sfr definition 21.8. smb1adr: smbus1 slave address ......... ............ ............ ......... 216 sfr definition 21.9. smb1adm: smbus1 slave address mask ........... ............ ......... 217 sfr definition 21.10. smb0dat: sm bus data .............. ................ ................. ........... 218 sfr definition 21.11. smb1dat: sm bus data .............. ................ ................. ........... 219 sfr definition 22.1. scon0: serial port 0 control .... ............. .............. ............ ......... 234 sfr definition 22.2. sbuf0: seri al (uart0) port data buffer . ............ ............ ......... 235 sfr definition 23.1. scon 1: uart1 control ...... .............. ............... .............. ........... 242 sfr definition 23.2. smod 1: uart1 mode ........... .............. .............. .............. ......... 243 sfr definition 23.3. sbuf1: uart 1 data buffer ....... ................. ................ .............. 244 sfr definition 23.4. sbcon1: ua rt1 baud rate generator c ontrol ........ .............. 245 sfr definition 23.5. sbrlh1: uart1 baud rate generator high byte ................... 245 sfr definition 23.6. sbrll1: uart1 baud rate generator low byte ....... .............. 246 sfr definition 24.1. spi0cfg: spi 0 configuration ....... ................ ................. ........... 254 sfr definition 24.2. spi0cn: spi0 control ......... .............. ............... .............. ........... 255 sfr definition 24.3. spi0ckr: spi 0 clock rate ........... ................ ................. ........... 256 sfr definition 24.4. spi0dat: spi0 data ................ .............. .............. ............ ......... 256 sfr definition 25.1. ckcon: clock control ............... ................. ................ .............. 261 sfr definition 25.2. ckcon1: clo ck control 1 .......... ................. ................ .............. 262 sfr definition 25.3. tcon: timer c ontrol ........... .............. ............... .............. ........... 267 sfr definition 25.4. tmod: timer mode ............. .............. ............... .............. ........... 268 sfr definition 25.5. tl0: timer 0 low byte ......... .............. ............... .............. ........... 269 sfr definition 25.6. tl1: timer 1 low byte ......... .............. ............... .............. ........... 269 sfr definition 25.7. th0: timer 0 high byte .............. ................. ................ .............. 270 sfr definition 25.8. th1: timer 1 high byte .............. ................. ................ .............. 270 sfr definition 25.9. tmr2cn: time r 2 control .......... ................. ................ .............. 275 sfr definition 25.10. tmr2rll: timer 2 reload regist er low byte ...... .................. 276 sfr definition 25.11. tmr2rlh: timer 2 reload regi ster high byte .... .................. 276 sfr definition 25.12. tmr2l: time r 2 low byte ........ ................. ................ .............. 276 sfr definition 25.13. tmr2h timer 2 high byte ........... ................ ................. ........... 277 sfr definition 25.14. tmr3cn: timer 3 control .... .............. .............. .............. ......... 282
rev. 1.0 15 c8051f380/1/2/3/4/5/6/7 sfr definition 25.15. tmr3rll: timer 3 reload regist er low byte ...... .................. 283 sfr definition 25.16. tmr3rlh: timer 3 reload regi ster high byte .... .................. 283 sfr definition 25.17. tmr3l: time r 3 low byte ........ ................. ................ .............. 283 sfr definition 25.18. tmr3h timer 3 high byte ........... ................ ................. ........... 284 sfr definition 25.19. tmr4cn: timer 4 control .... .............. .............. .............. ......... 287 sfr definition 25.20. tmr4rll: timer 4 reload regist er low byte ...... .................. 288 sfr definition 25.21. tmr4rlh: timer 4 reload regi ster high byte .... .................. 288 sfr definition 25.22. tmr4l: time r 4 low byte ........ ................. ................ .............. 288 sfr definition 25.23. tmr4h timer 4 high byte ........... ................ ................. ........... 289 sfr definition 25.24. tmr5cn: timer 5 control .... .............. .............. .............. ......... 292 sfr definition 25.25. tmr5rll: timer 5 reload regist er low byte ...... .................. 293 sfr definition 25.26. tmr5rlh: timer 5 reload regi ster high byte .... .................. 293 sfr definition 25.27. tmr5l: time r 5 low byte ........ ................. ................ .............. 293 sfr definition 25.28. tmr5h timer 5 high byte ........... ................ ................. ........... 294 sfr definition 26.1. pca0cn: pca control ........ .............. ............... .............. ........... 308 sfr definition 26.2. pca0md: pca mode .......... .............. ............... .............. ........... 309 sfr definition 26.3. pca0cpmn : pca capture/compare mode .. ................. ........... 310 sfr definition 26.4. pca0l: pca counter/timer low byte ..... ............ ............ ......... 311 sfr definition 26.5. pca0h: pc a counter/timer high byte .... ............ ............ ......... 311 sfr definition 26.6. pca0cpln: pca capture module low byte ............... .............. 312 sfr definition 26.7. pca0cphn: pca capture module high byte ............. .............. 312 c2 register definition 27.1. c2ad d: c2 address ....... ................. ................ .............. 313 c2 register definition 27.2. deviceid: c2 device id ............ .............. ............ ......... 314 c2 register definition 27.3. revid: c2 revision id ............... .............. ............ ......... 314 c2 register definition 27.4. fpctl: c2 flas h programming control .. ............. ......... 315 c2 register definition 27.5. fpdat: c2 flas h programming data ..... .............. ......... 315
c8051f380/1/2/3/4/5/6/7 16 rev. 1.0 1. system overview c8051f380/1/2/3/4/5/6/7 devices are fully integrated mixed-si gnal system-on-a-ch ip mcus. highlighted features are listed below. refer to table 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 48 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? universal serial bus (usb) function controller wit h eight flexible endpoint pipes, integrated transceiver, and 1 kb fifo ram ? supply voltage regulator ? true 10-bit 500 ksps differential / single-ended adc with analog multiplexer ? on-chip voltage reference and temperature sensor ? on-chip voltage comparators (2) ? precision internal calibrate d 48 mhz internal oscillator ? internal low-frequency oscillato r for additional power savings ? up to 64 kb of on-chip flash memory ? up to 4352 bytes of on-chip ram (256 + 4 kb) ? external memory interface (emif) available on 48-pin versions. ? 2 i 2 c/smbus, 2 uarts, and enhanced spi seri al interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with five capture/compare modules and watchdog timer function ? on-chip power-on reset, v dd monitor, and missing clock detector ? up to 40 port i/o (5 v tolerant) with on-chip powe r-on reset, v dd monitor, voltage regulator, watc hdog timer, and clock oscillator, c8051f380/1/2/3/4/5/6/7 devices are truly stand-al one system-on-a-chip solutions. the flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) development interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digi tal peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in-system debugging with- out occupying package pins. each device is specified for 2.7?5.25 v operation over the industrial temperature range (?40 to +85 c). for voltages above 3.6 v, the on-chip voltage regulator must be used. a minimum of 3.0 v is required for usb communication. the port i/o and rst pins are tolerant of input si gnals up to 5 v. c8051f380/1/2/3/ 4/5/6/7 devices are available in 48-pin tqfp, 32-pin lqfp, or 32-pin qfn packages. see table 1.1, ?prod- uct selection guide,? on page 17 for feature and package choices.
rev. 1.0 17 c8051f380/1/2/3/4/5/6/7 table 1.1. product selection guide ordering part number mips (peak) flash memory (bytes) ram calibrated internal oscillator low frequency oscillator usb with 1k endpoint ram supply voltage regulator smbus/i2c enhanced spi uarts timers (16-bit) programmable counter array digital port i/o external memory interface (emif) 10-bit 500ksps adc temperature sensor voltage reference analog comparators package c8051f380-gq 48 64k 4352 ???? 2 ? 26 ? 40 ???? 2tqfp48 c8051f381-gq 48 64k 4352 ???? 2 ? 26 ? 25 ? ??? 2lqfp32 c8051f381-gm 48 64k 4352 ???? 2 ? 26 ? 25 ? ??? 2qfn32 c8051f382-gq 48 32k 2304 ???? 2 ? 26 ? 40 ???? 2tqfp48 c8051f383-gq 48 32k 2304 ???? 2 ? 26 ? 25 ? ??? 2lqfp32 c8051f383-gm 48 32k 2304 ???? 2 ? 26 ? 25 ? ??? 2qfn32 c8051f384-gq 48 64k 4352 ???? 2 ? 26 ? 40 ? ???2 tqfp48 C8051F385-GQ 48 64k 4352 ???? 2 ? 26 ? 25 ????2 lqfp32 c8051f385-gm 48 64k 4352 ???? 2 ? 26 ? 25 ????2 qfn32 c8051f386-gq 48 32k 2304 ???? 2 ? 26 ? 40 ? ???2 tqfp48 c8051f387-gq 48 32k 2304 ???? 2 ? 26 ? 25 ????2 lqfp32 c8051f387-gm 48 32k 2304 ???? 2 ? 26 ? 25 ????2 qfn32
c8051f380/1/2/3/4/5/6/7 18 rev. 1.0 figure 1.1. c8051f380/2/4/6 block diagram analog peripherals 10-bit 500ksps adc a m u x temp sensor 2 comparators + - vref vdd cp0 vdd + - cp1 vref debug / programming hardware port 0 drivers p0.0 ain0 - ain19 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3, 4, 5 pca/wdt smbus1 uart1 spi p0.1 p0.2 p0.3 p0.4 p0.5 p0.6/xtal1 p0.7/xtal2 port 1 drivers port 2 drivers port 3 drivers port 4 drivers p1.0 p1.1 p1.2 p1.3 p1.4/cnvstr p1.5/vref p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 p4.6 p4.7 supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator clock recovery usb peripheral controller 1k byte ram full / low speed transceiver external memory interface control address data p1 p2 / p3 p4 sfr bus voltage regulators d+ d- vbus vdd vreg gnd c2ck/rst reset c2d cip-51 8051 controller core 64/32k byte isp flash program memory 256 byte ram 4/2k byte xram smbus0
rev. 1.0 19 c8051f380/1/2/3/4/5/6/7 figure 1.2. c8051f381/3/5/7 block diagram analog peripherals 10-bit 500 ksps adc a m u x temp sensor 2 comparators + - vref vdd cp0 vdd + - cp1 vref debug / programming hardware port 0 drivers p0.0 ain0 - ain20 port i/o configuration digital peripherals priority crossbar decoder crossbar control power-on reset power net uart0 timers 0, 1, 2, 3, 4, 5 pca/wdt spi p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref port 1 drivers port 2 drivers port 3 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d supply monitor system clock setup external oscillator internal oscillator xtal1 xtal2 low freq. oscillator clock recovery usb peripheral controller 1 kb ram full / low speed transceiver sfr bus d+ d- vbus vdd vreg gnd c2ck/rst reset cip-51 8051 controller core 64/32 kb isp flash program memory 256 byte ram 4/2 kb xram c2d smbus1 smbus0 voltage regulators uart1
c8051f380/1/2/3/4/5/6/7 20 rev. 1.0 2. c8051f34x compatibility the c8051f38x family is designed to be a pin and code compatible replacement for the c8051f34x device family, with an enhanced feature set. the c805 1f38x device should function as a drop-in replace- ment for the c8051f34x devices in most applications . table 2.1 lists recommended replacement part num- bers for c8051f34x devices. see ?2.1. hardware incompatibilities? to determine if any changes are necessary when upgrading an existing c8051f34x design to the c8051f38x. table 2.1. c8051f38x replacement part numbers c8051f34x part number c8051f38x part number c8051f340-gq c8051f380-gq c8051f341-gq c8051f382-gq c8051f342-gq c8051f381-gq c8051f342-gm c8051f381-gm c8051f343-gq c8051f383-gq c8051f343-gm c8051f383-gm c8051f344-gq c8051f380-gq c8051f345-gq c8051f382-gq c8051f346-gq c8051f381-gq c8051f346-gm c8051f381-gm c8051f347-gq c8051f383-gq c8051f347-gm c8051f383-gm c8051f348-gq c8051f386-gq c8051f349-gq c8051f387-gq c8051f349-gm c8051f387-gm c8051f34a-gq c8051f381-gq c8051f34a-gm c8051f381-gm c8051f34b-gq c8051f383-gq c8051f34b-gm c8051f383-gm c8051f34c-gq c8051f384-gq c8051f34d-gq C8051F385-GQ
rev. 1.0 21 c8051f380/1/2/3/4/5/6/7 2.1. hardware incompatibilities while the c8051f38x family includes a number of new features not found on the c8051f34x family, there are some differences that should be considered for any design port. ? clock multiplier : the c8051f38x does not include the 4x clock multiplier from the c8051f34x device families. this change only impacts systems which use the clock multiplier in conjunction with an external oscillator source. ? external oscillator c and rc modes : the c and rc modes of the osc illator have a di vide-by-2 stage on the c8051f38x to aid in noise immunity. this was not present on the c8051f34x device family, and any clock generated with c or rc mode will change accordingly. ? fab technology : the c8051f38x is manufactured using a different technology process than the c8051f34x. as a result, ma ny of the electrical performance pa rameters will have subtle differences. these differences should not affect most systems but it is nonetheless im portant to review the electrical parameters for any blocks that are used in the design, and ensure they are compatible with the existing hardware.
c8051f380/1/2/3/4/5/6/7 22 rev. 1.0 3. pinout and p ackage definitions table 3.1. pin definitions for the c8051f380/1/2/3/4/5/6/7 name pin numbers type description 48-pin 32-pin v dd 10 6 power in power out 2.7?3.6 v power supply voltage input. 3.3 v voltage regulator output. gnd 7 3 ground. rst / c2ck 13 9 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. clock signal for the c2 debug interface. c2d 14 ? d i/o bi-directional data signal for the c2 debug interface. p3.0 / c2d ? 10 d i/o d i/o port 3.0. see section 19 for a complete description of port 3. bi-directional data signal for the c2 debug interface. regin 11 7 power in 5 v regulator input. this pin is the input to the on-chip volt- age regulator. vbus 12 8 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indi- cates a usb network connection. d+ 8 4 d i/o usb d+. d- 9 5 d i/o usb d?. p0.0 6 2 d i/o or a in port 0.0. see section 19 for a complete description of port 0. p0.1 5 1 d i/o or a in port 0.1. p0.2 4 32 d i/o or a in port 0.2. p0.3 3 31 d i/o or a in port 0.3. p0.4 2 30 d i/o or a in port 0.4. p0.5 1 29 d i/o or a in port 0.5. p0.6 48 28 d i/o or a in port 0.6. p0.7 47 27 d i/o or a in port 0.7.
rev. 1.0 23 c8051f380/1/2/3/4/5/6/7 p1.0 46 26 d i/o or a in port 1.0. see section 19 for a complete description of port 1. p1.1 45 25 d i/o or a in port 1.1. p1.2 44 24 d i/o or a in port 1.2. p1.3 43 23 d i/o or a in port 1.3. p1.4 42 22 d i/o or a in port 1.4. p1.5 41 21 d i/o or a in port 1.5. p1.6 40 20 d i/o or a in port 1.6. p1.7 39 19 d i/o or a in port 1.7. p2.0 38 18 d i/o or a in port 2.0. see section 19 for a complete description of port 2. p2.1 37 17 d i/o or a in port 2.1. p2.2 36 16 d i/o or a in port 2.2. p2.3 35 15 d i/o or a in port 2.3. p2.4 34 14 d i/o or a in port 2.4. p2.5 33 13 d i/o or a in port 2.5. p2.6 32 12 d i/o or a in port 2.6. p2.7 31 11 d i/o or a in port 2.7. p3.0 30 ? d i/o or a in port 3.0. see section 19 for a complete description of port 3. p3.1 29 ? d i/o or a in port 3.1. p3.2 28 ? d i/o or a in port 3.2. table 3.1. pin definitions for the c8051f380/1/2/3/4/5/6/7 (continued) name pin numbers type description 48-pin 32-pin
c8051f380/1/2/3/4/5/6/7 24 rev. 1.0 p3.3 27 ? d i/o or a in port 3.3. p3.4 26 ? d i/o or a in port 3.4. p3.5 25 ? d i/o or a in port 3.5. p3.6 24 ? d i/o or a in port 3.6. p3.7 23 ? d i/o or a in port 3.7. p4.0 22 ? d i/o or a in port 4.0. see section 19 for a complete description of port 4. p4.1 21 ? d i/o or a in port 4.1. p4.2 20 ? d i/o or a in port 4.2. p4.3 19 ? d i/o or a in port 4.3. p4.4 18 ? d i/o or a in port 4.4. p4.5 17 ? d i/o or a in port 4.5. p4.6 16 ? d i/o or a in port 4.6. p4.7 15 ? d i/o or a in port 4.7. table 3.1. pin definitions for the c8051f380/1/2/3/4/5/6/7 (continued) name pin numbers type description 48-pin 32-pin
rev. 1.0 25 c8051f380/1/2/3/4/5/6/7 figure 3.1. tqfp-48 pinout diagram (top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 vbus p2.2 p2.0 p1.7 p1.6 p1.2 p2.4 p2.3 p3.5 p3.4 p3.2 p3.1 p2.1 p0.6 p3.3 p0.7 p0.2 d- regin p0.3 p3.0 p1.4 p1.5 p0.5 p1.1 p1.0 p0.4 p1.3 13 14 15 16 17 18 19 20 21 22 23 24 p2.6 p2.5 c8051f380/2/4/6-gq top view gnd d+ p0.1 p0.0 vdd p2.7 p3.6 p4.1 p4.0 p3.7 p4.2 p4.5 p4.4 p4.3 p4.6 rst / c2ck c2d p4.7
c8051f380/1/2/3/4/5/6/7 26 rev. 1.0 figure 3.2. tqfp-48 package diagram table 3.2. tqfp-48 package dimensions dimension min nom min dimension min nom min a ??? e 9.00 bsc a1 0.05 ? 0.05 e1 7.00 bsc a2 0.95 1.00 0.95 l 0.45 0.60 0.45 b 0.17 0.22 0.17 aaa 0.20 c 0.09 ? 0.09 bbb 0.20 d 9.00 bsc ccc 0.08 d1 7.00 bsc ddd 0.08 e 0.50 bsc q 0 3.5 0 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline ms-026, variation abc. 4. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.0 27 c8051f380/1/2/3/4/5/6/7 figure 3.3. tqfp-48 recommended pcb land pattern table 3.3. tqfp-48 pcb land pattern dimensions dimension min max c1 8.30 8.40 c2 8.30 8.40 e0.50 bsc x1 0.20 0.30 y1 1.40 1.50 notes: general: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly: 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f380/1/2/3/4/5/6/7 28 rev. 1.0 figure 3.4. lqfp-32 pinout diagram (top view) 1 vbus p1.2 p1.7 p1.4 p1.3 p1.5 d+ d? gnd p0.1 p0.0 p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 c8051f381/3/5/7-gq top view vdd regin rst / c2ck p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2
rev. 1.0 29 c8051f380/1/2/3/4/5/6/7 figure 3.5. lqfp-32 package diagram table 3.4. lqfp-32 package dimensions dimension min nom max dimension min nom max a ? ? 1.60 e 9.00 bsc a1 0.05 ? 0.15 e1 7.00 bsc a2 1.35 1.40 1.45 l 0.45 0.60 0.75 b 0.300.370.45 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc ccc 0.10 d1 7.00 bsc ddd 0.20 e 0.80 bsc q 03.57 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jede c outline ms-026, variation bba. 4. the recommended card reflow profile is per the je dec/ipc j-std-020 specif ication for small body components.
c8051f380/1/2/3/4/5/6/7 30 rev. 1.0 figure 3.6. lqfp-32 recommended pcb land pattern table 3.5. lqfp-32 pcb land pattern dimensions dimension min max c1 8.40 8.50 c2 8.40 8.50 e0.80 bsc x1 0.40 0.50 y1 1.25 1.35 notes: general: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design: 4. a stainless steel, laser-cut and electro- polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly: 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
rev. 1.0 31 c8051f380/1/2/3/4/5/6/7 figure 3.7. qfn-32 pinout diagram (top view) 25 p1.1 17 p2.1 16 p2.2 8 vbus 32 31 30 29 28 27 26 1 2 3 4 5 6 7 9 10 11 12 13 14 15 24 23 22 21 20 19 18 gnd (optional) c8051f381/3/5/7-gm top view p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 gnd d+ d? vdd regin rst / c2ck p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2
c8051f380/1/2/3/4/5/6/7 32 rev. 1.0 figure 3.8. qfn-32 package drawing table 3.6. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 e2 3.20 3.30 3.40 a1 0.00 0.02 0.05 l 0.30 0.40 0.50 b 0.18 0.25 0.30 l1 0.00 ? 0.15 d 5.00 bsc aaa 0.15 d2 3.20 3.30 3.40 bbb 0.10 e 0.50 bsc ddd 0.05 e 5.00 bsc eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, and l which are toleranced per supplier designation. 4. the recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components.
rev. 1.0 33 c8051f380/1/2/3/4/5/6/7 figure 3.9. qfn-32 recommended pcb land pattern table 3.7. qfn-32 pcb land pattern dimensions dimension min max dimension min max c1 4.80 4.90 x2 3.20 3.40 c2 4.80 4.90 y1 0.75 0.85 e 0.50 bsc y2 3.20 3.40 x1 0.20 0.30 notes: general: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design: 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design: 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 7. a 3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure the proper paste volume. card assembly: 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per t he jedec/ipc j-std-020 specification for small body components.
c8051f380/1/2/3/4/5/6/7 34 rev. 1.0 4. electrical characteristics 4.1. absolute m aximum specifications table 4.1. absolute maximum ratings parameter conditions min typ max units junction temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst or any port i/o pin with respect to gnd v dd > 2.2 v v dd < 2.2 v ?0.3 ?0.3 ? ? 5.8 v dd + 3.6 v v voltage on v dd with respect to gnd regulator1 in normal mode regulator1 in bypass mode ?0.3 ?0.3 ? ? 4.2 1.98 v v maximum total current through v dd or gnd ??500ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listi ngs of this specification is not im plied. exposure to maximum rating conditions for extended periods may affect device reliability.
rev. 1.0 35 c8051f380/1/2/3/4/5/6/7 4.2. electrical characteristics table 4.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units digital supply voltage 1 v rst 1 3.3 3.6 v digital supply ram data retention voltage ?1.5? v sysclk (system clock) 2 0?48mhz specified operating temperature range ?40 ? +85 c digital supply current?cpu active (normal mode, fetching instructions from flash) i dd 3 sysclk = 48 mhz, v dd = 3.3 v ? 12 14 ma sysclk = 24 mhz, v dd = 3.3 v ? 7 8 ma sysclk = 1 mhz, v dd = 3.3 v ? 0.45 0.85 ma sysclk = 80 khz, v dd = 3.3 v ? 280 ? a digital supply current?cpu inactive (idle mode , not fetching instructions from flash) idle i dd 3 sysclk = 48 mhz, v dd = 3.3 v ? 6.5 8 ma sysclk = 24 mhz, v dd = 3.3 v ? 3.5 5 ma sysclk = 1 mhz, v dd = 3.3 v ? 0.35 ? ma sysclk = 80 khz, v dd = 3.3 v ? 220 ? a digital supply current (stop or suspend mode, shut- down) oscillator not running (stop mode), internal regulators off, v dd = 3.3 v ?1?a oscillator not running (stop or sus- pend mode), reg0 and reg1 both in low power mode, v dd = 3.3 v. ?100? a oscillator not running (stop or sus- pend mode), reg0 off, v dd = 3.3 v. ?150? a digital supply current for usb module (usb active mode 4 ) usb clock = 48 mhz, v dd = 3.3 v ? 8 ? ma notes: 1. usb requires 3.0 v minimum supply voltage. 2. sysclk must be at least 32 khz to enable debugging. 3. includes normal mode bias current for reg0 and reg1. do es not include current from internal oscillators, usb, or other analog peripherals. 4. an additional 220ua is sourced by the d+ or d- pul l-up to the usb bus when the usb pull-up is active.
c8051f380/1/2/3/4/5/6/7 36 rev. 1.0 table 4.3. port i/o dc electrical characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ?0.7 v dd ?0.1 ? ? ? v dd ?0.8 ? ? ? v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage 2.0 ? ? v input low voltage ? ? 0.8 v input leakage current weak pullup off weak pullup on, v in = 0 v ? ? ? 15 1 50 a table 4.4. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 v to 3.6 v ??0.6v rst input high voltage 0.7 x v dd ?? v rst input low voltage ? ? 0.3 x v dd v rst input pullup current rst = 0.0 v ?1540a v dd monitor threshold (v rst ) 2.60 2.65 2.70 v missing clock detector time- out time from last system clock rising edge to reset initiation 80 580 800 s reset time delay delay between release of any reset source and code execution at location 0x0000 ??250s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time ? ? 100 s v dd monitor supply current ? 15 50 a
rev. 1.0 37 c8051f380/1/2/3/4/5/6/7 table 4.5. internal voltage regulator electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units voltage regulator (reg0) input voltage range 1 2.7 ? 5.25 v output voltage (v dd ) 2 output current = 1 to 100 ma 3.0 3.3 3.6 v output current 2 ??100ma dropout voltage (v do ) 3 ?1?mv/ma voltage regulator (reg1) input voltage range 1.8 ? 3.6 v notes: 1. input range specified for regulation. when an exte rnal regulator is used, should be tied to v dd . 2. output current is total regulator output, including any current required by th e c8051f380/1/ 2/3/4/5/6/7. 3. the minimum input voltage is 2.70 v or v dd + v do (max load), whichever is greater. table 4.6. flash electrical characteristics parameter conditions min typ max units flash size c8051f380/1/4/5* c8051f382/3/6/7 65536* 32768 ??bytes bytes endurance 20k 100k ? erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 10 15 20 s note: 1024 bytes at location 0xfc00 to 0xffff are not available for program storage
c8051f380/1/2/3/4/5/6/7 38 rev. 1.0 table 4.7. internal high-frequency oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied; using factory-calibrated settings. parameter conditions min typ max units oscillator frequency ifcn = 11b 47.3 48 48.7 mhz oscillator supply current (from v dd ) 25 c, v dd = 3.0 v, oscicn.7 = 1, ocsicn.5 = 0 ? 900 ? a power supply sensitivity constant temperature ? 110 ? ppm/v temperature sensitivity constant supply ? 25 ? ppm/c table 4.8. internal low-frequency oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied; using factory-calibrated settings. parameter conditions min typ max units oscillator frequency oscld = 11b 75 80 85 khz oscillator supply current (from v dd ) 25 c, v dd = 3.0 v, osclcn.7 = 1 ?4?a power supply sensitivity constant temperature ? 0.05 ? %/v temperature sensitivity constant supply ? 65 ? ppm/c table 4.9. external oscillator electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c unless otherwise specified. parameter conditions min typ max units external crystal frequency 0.02 ? 30 mhz external cmos oscillator frequency 0?48mhz
rev. 1.0 39 c8051f380/1/2/3/4/5/6/7 table 4.10. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), pga gain = 1, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guar anteed monotonic ? 0.5 1 lsb offset error ?2 0 2 lsb full scale error ?5 ?2 0 lsb offset temperature coefficient ? 0.005 ? lsb/c dynamic performance (10 khz sine-wave single- ended input, 1 db below full scale, 500 ksps) signal-to-noise plus distortion 55 58 ? db total harmonic distortion up to the 5th harmonic ? ?73 ? db spurious-free dynamic range ? 78 ? db conversion rate sar conversion clock ? ? 8.33 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks clocks track/hold acquisition time 300 ? ? ns throughput rate ? ? 500 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) 0 ? vref v differential (ain+ ? ain?) ?vref ? vref v absolute pin voltage with respect to gnd single ended or differential 0 ? v dd v sampling capacitance gain = 1x (amp0gn0 = 1) gain = 0.5x (amp0gn0 = 0) ? ? 30 28 ? ? pf pf input multiplexer impedance ? 5 ? k ? power specifications power supply current (v dd supplied to adc0) operating mode, 500 ksps ? 750 880 a power supply rejection ? 1 ? mv/v note: represents one standard deviation from the mean.
c8051f380/1/2/3/4/5/6/7 40 rev. 1.0 table 4.11. temperature sensor electrical characteristics v dd = 3.0 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 0.5 ? c slope ? 2.87 ? mv/c slope error* ? 120 ? v/c offset temp = 0 c ? 764 ? mv offset error* temp = 0 c ? 15 ? mv note: represents one standard deviation from the mean. table 4.12. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.38 2.42 2.46 v vref short-circuit current ? ? 8 ma vref temperature coefficient ?35?ppm/c load regulation load = 0 to 200 a to gnd ? 1.5 ? ppm/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic bypass ? 3 ? ms vref turn-on time 2 0.1 f ceramic bypass ? 100 ? s power supply rejection ? 140 ? ppm/v external reference (refbe = 0) input voltage range 1 ? v dd v input current sample rate = 500 ksps; vref = 3.0 v ? 9 ? a power specifications supply current ? 75 ? a
rev. 1.0 41 c8051f380/1/2/3/4/5/6/7 table 4.13. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 100 ? ns cp0+ ? cp0? = ?100 mv ? 250 ? ns response time: mode 1, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 175 ? ns cp0+ ? cp0? = ?100 mv ? 500 ? ns response time: mode 2, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 320 ? ns cp0+ ? cp0? = ?100 mv ? 1100 ? ns response time: mode 3, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 1050 ? ns cp0+ ? cp0? = ?100 mv ? 5200 ? ns common-mode rejection ratio ? 1.5 4 mv/v positive hysteresis 1 cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 2 5 10 mv positive hysteresis 3 cp0hyp1?0 = 10 7 10 20 mv positive hysteresis 4 cp0hyp1?0 = 11 15 20 30 mv negative hysteresis 1 cp0hyn1?0 = 00 ? 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 2 5 10 mv negative hysteresis 3 cp0hyn1?0 = 10 7 10 20 mv negative hysteresis 4 cp0hyn1?0 = 11 15 20 30 mv inverting or non- inverting input voltage range ?0.25 ? v dd + 0.25 v input capacitance ? 4 ? pf input bias current ? 0.001 ? na input offset voltage ?5 ? +5 mv power supply power supply rejection ? 0.1 ? mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 20 ? a mode 1 ? 10 ? a mode 2 ? 4 ? a mode 3 ? 1 ? a note: vcm is the common-mode voltage on cp0+ and cp0?.
c8051f380/1/2/3/4/5/6/7 42 rev. 1.0 table 4.14. usb transceiver electrical characteristics v dd = 3.0 v to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units transmitter output high voltage (v oh )2.8??v output low voltage (v ol )??0.8v vbus detection input low voltage ?? 1.0 v vbus detection input high voltage 3.0 ? ? v output crossover point (v crs ) 1.3 ? 2.0 v output impedance (z drv ) driving high driving low ? ? 38 38 ? ? w pull-up resistance (r pu ) full speed (d+ pull-up) low speed (d? pull-up) 1.425 1.5 1.575 k ? output rise time (t r ) low speed full speed 75 4 ? ? 300 20 ns output fall time (t f ) low speed full speed 75 4 ? ? 300 20 ns receiver differential input sensitivity (v di ) | (d+) ? (d?) | 0.2 ? ? v differential input common mode range (v cm ) 0.8 ? 2.5 v input leakage current (i l ) pullups disabled ? <1.0 ? a note: refer to the usb specification for timing diagrams and symbol definitions.
rev. 1.0 43 c8051f380/1/2/3/4/5/6/7 5. 10-bit adc (adc0, c8051f380/1/2/3 only) adc0 on the c8051f380/1/2/3 is a 500 ksps, 10-bit successive-approximation-register (sar) adc with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a programmable window detector. the adc is fully configurable under software control via special functi on registers. the adc may be con- figured to measure various different signals using the analog multiplexer described in section ?5.4. adc0 analog multiplexer (c8051f380/1/2/3 only)? on page 54. the voltage reference for the adc is selected as described in section ?6. voltage reference options? on page 57. the adc0 subsystem is enabled only when the ad0en bit in the adc0 co ntrol register (adc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. figure 5.1. adc0 functional block diagram adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic gnd 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p5 amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n5 amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 ain+ ain- vref positive input (ain+) amux vdd negative input (ain-) amux temp sensor port i/o pins* port i/o pins* * 21 selections on 32-pin package 32 selections on 48-pin package timer 4 overflow timer 5 overflow 110 111
c8051f380/1/2/3/4/5/6/7 44 rev. 1.0 5.1. output code formatting the conversion code format differs between single -ended and differential modes. the registers adc0h and adc0l contain the high and low bytes of the outpu t conversion code from the adc at the completion of each conversion. data can be right-justified or left -justified, depending on the setting of the ad0ljst bit (adc0cn.0). when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. ex ample codes are shown belo w for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to 0. when in differential mode, conversion codes are re presented as 10-bit signed 2s complement numbers. inputs are measured from ?vref to vref x 511/512. example codes are shown below for both right-jus- tified and left-justified data. for right-justified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to 0. 5.2. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 5.2.1. starting a conversion a conversion can be initiated in one of several ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conver sions may be initiated by one of the following: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., ti med continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow 7. a timer 4 overflow 8. a timer 5 overflow writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt input voltage (single-ended) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage (differential) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000
rev. 1.0 45 c8051f380/1/2/3/4/5/6/7 flag (ad0int). note: when polling for adc conversi on completions, the adc0 interrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2, 3, 4, or 5 overfl ows are used as the conversion source, low byte over- flows are used if the timer is in 8-bit mode; high byte overflows are used if the timer is in 16-bit mode. see section ?25. timers? on page 260 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port i/o pin. when the cnvstr input is used as t he adc0 conversion source, the associated pin should be skipped by the digi- tal crossbar. see section ?19. port input/output? on page 150 for details on port i/o configuration.
c8051f380/1/2/3/4/5/6/7 46 rev. 1.0 5.2.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversi on is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a track- ing period of 3 sar clocks (after the start-of-convers ion signal). when the cnvstr signal is used to initi- ate conversions in low-power tracking mode, adc0 tr acks only when cnvstr is low; conversion begins on the rising edge of cnvstr. see figure 5.2 for tr ack and convert timing details. tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track-and-hold mode is also useful when amux settings are freq uently changed, due to the settling time requirements described in section ?5.2.3. settling time requirements? on page 47. figure 5.2. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks 123456789 1 0 1 1 1 2 123456789 sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 1 0 1 1 1 3 1 4 1 0 1 1
rev. 1.0 47 c8051f380/1/2/3/4/5/6/7 5.2.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per- formed. this tracking time is determined by the am ux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks are used for tracking at the start of every conversion. for most applications, these three sar clocks will meet the mini mum tracking time requirements. figure 5.3 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5 .1. see table 4.10 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). figure 5.3. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? ln = r mux rc input = r mux * c sample r mux c sample c sample mux select mux select differential mode px.x px.x r mux c sample rc input = r mux * c sample mux select single-ended mode px.x
c8051f380/1/2/3/4/5/6/7 48 rev. 1.0 sfr address = 0xbc; sfr page = all pages sfr definition 5.1. adc0cf : adc0 configuration bit76543210 name ad0sc[4:0] ad0ljst reserved type r/w r/w r/w reset 11111000 bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table. note: if the memory power controller is enabled (mpce = '1'), ad0sc must be set to at least "00001" for proper adc operation. 2ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. note: the ad0ljst bit is only valid for 10-bit mode (ad08be = 0). 1:0 reserved must write 00b. ad0sc sysclk clk sar ------------ ---------- - 1 ? =
rev. 1.0 49 c8051f380/1/2/3/4/5/6/7 sfr address = 0xbe; sfr page = all pages sfr address = 0xbd; sfr page = all pages sfr definition 5.2. adc0h: adc0 data word msb bit76543210 name adc0h[7:0] type r/w reset 00000000 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7 ? 2 will read 000000b. bits 1 ? 0 are the upper 2 bits of the 10- bit adc0 data word. for ad0ljst = 1: bits 7 ? 0 are the most-significant bits of the 10-bit adc0 data word. sfr definition 5.3. adc0l: adc0 data word lsb bit76543210 name adc0l[7:0] type r/w reset 00000000 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7 ? 0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7 ? 6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will read 000000b.
c8051f380/1/2/3/4/5/6/7 50 rev. 1.0 sfr address = 0xe8; sfr page = all pages; bi t-addressable sfr definition 5.4. adc0cn: adc0 control bit76543210 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con- version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: delayed track mode: when adc0 is enabled, input is tracked when a conversion is not in progress. a start-of-conversion sign al initiates three sar clocks of additional tracking, and then begins the conversion. note that there is not a tracking delay when cnvstr is used (ad0cm[2:0] = 100). 5ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in prog- ress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm[2 : 0] = 000b 3 ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2:0] adc0 start of conversion mode select. 000: adc0 start-of-conversion s ource is write of 1 to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101: adc0 start-of-conversion source is overflow of timer 3. 110: adc0 start-of-conversion source is overflow of timer 4. 111: adc0 start-of-conversion source is overflow of timer 5.
rev. 1.0 51 c8051f380/1/2/3/4/5/6/7 5.3. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr address = 0xc4; sfr page = all pages sfr address = 0xc3; sfr page = all pages sfr definition 5.5. adc0gth: adc 0 greater-than data high byte bit76543210 name adc0gth[7:0] type r/w reset 11111111 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 5.6. adc0gtl: adc 0 greater-than data low byte bit76543210 name adc0gtl[7:0] type r/w reset 11111111 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits.
c8051f380/1/2/3/4/5/6/7 52 rev. 1.0 sfr address = 0xc6; sfr page = all pages sfr address = 0xc5; sfr page = all pages sfr definition 5.7. adc0lth: adc0 less-than data high byte bit76543210 name adc0lth[7:0] type r/w reset 00000000 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 5.8. adc0ltl: a dc0 less-than data low byte bit76543210 name adc0ltl[7:0] type r/w reset 00000000 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits.
rev. 1.0 53 c8051f380/1/2/3/4/5/6/7 5.3.1. window detector example figure 5.4 shows two example window comparison s for right-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if th e adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right exam ple, and ad0wint interr upt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.5 shows an example using left-justi- fied data with the same comparison values. figure 5.4. adc window compare example: right-justified data figure 5.5. adc window compare example: left-justified data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
c8051f380/1/2/3/4/5/6/7 54 rev. 1.0 5.4. adc0 analog mult iplexer (c8051f380/1/2/3 only) amux0 selects the positive and negative inputs to th e adc. the positive input (ain+) can be connected to individual port pins, the on-chip temperature sensor, or the positive power supply (v dd ). the negative input (ain-) can be connected to individual port pi ns, vref, or gnd. when gnd is selected as the nega- tive input, adc0 operates in sing le-ended mode; at all other times, adc0 operates in differential mode. the adc0 input channels are selected in the amx0p and amx0n registers as described in sfr definition 5.9 and sfr definition 5.10. important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by th e digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in register pnmdin. to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?19. port input/output? on page 150 for more port i/o configuration details.
rev. 1.0 55 c8051f380/1/2/3/4/5/6/7 sfr address = 0xbb; sfr page = all pages sfr definition 5.9. amx0p: am ux0 positive channel select bit76543210 name amx0p[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 amx0p[5:0] amux0 positive input selection. amx0p 32-pin packages 48-pin packages amx0p 32-pin packages 48-pin packages 000000: p1.0 p2.0 010010: p0.1 p0.4 000001: p1.1 p2.1 010011: p0.4 p1.1 000010: p1.2 p2.2 010100: p0.5 p1.2 000011: p1.3 p2.3 010101: reserved p1.0 000100: p1.4 p2.5 010110: reserved p1.3 000101: p1.5 p2.6 010111: reserved p1.6 000110: p1.6 p3.0 011000: reserved p1.7 000111: p1.7 p3.1 011001: reserved p2.4 001000: p2.0 p3.4 011010: reserved p2.7 001001: p2.1 p3.5 011011: reserved p3.2 001010: p2.2 p3.7 011100: reserved p3.3 001011: p2.3 p4.0 011101: reserved p3.6 001100: p2.4 p4.3 011110: temp sensor temp sensor 001101: p2.5 p4.4 011111: v dd v dd 001110: p2.6 p4.5 100000: reserved p4.1 001111: p2.7 p4.6 100001: reserved p4.2 010000: p3.0 reserved 100010: reserved p4.7 010001: p0.0 p0.3 100011 - 111111: reserved reserved
c8051f380/1/2/3/4/5/6/7 56 rev. 1.0 sfr address = 0xba; sfr page = all pages sfr definition 5.10. amx0n: am ux0 negative channel select bit76543210 name amx0n[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 amx0n[5:0] amux0 negative input selection. amx0n 32-pin packages 48-pin packages amx0n 32-pin packages 48-pin packages 000000: p1.0 p2.0 010010: p0.1 p0.4 000001: p1.1 p2.1 010011: p0.4 p1.1 000010: p1.2 p2.2 010100: p0.5 p1.2 000011: p1.3 p2.3 010101: reserved p1.0 000100: p1.4 p2.5 010110: reserved p1.3 000101: p1.5 p2.6 010111: reserved p1.6 000110: p1.6 p3.0 011000: reserved p1.7 000111: p1.7 p3.1 011001: reserved p2.4 001000: p2.0 p3.4 011010: reserved p2.7 001001: p2.1 p3.5 011011: reserved p3.2 001010: p2.2 p3.7 011100: reserved p3.3 001011: p2.3 p4.0 011101: reserved p3.6 001100: p2.4 p4.3 011110: vref vref 001101: p2.5 p4.4 011111: gnd (single-ended measurement) gnd (single-ended measurement) 001110: p2.6 p4.5 100000: reserved p4.1 001111: p2.7 p4.6 100001: reserved p4.2 010000: p3.0 reserved 100010: reserved p4.7 010001: p0.0 p0.3 100011 - 111111: reserved reserved
rev. 1.0 57 c8051f380/1/2/3/4/5/6/7 6. voltage reference options the voltage reference multiplexer fo r the adc is configurable to use an externally connected voltage ref- erence, the on-chip reference voltage generator routed to the vref pin, the unregulated power supply voltage (v dd ), or the regulated 1.8 v internal supply (see figure 6.1). the refsl bit in the reference control register (ref0cn, sfr definition 6.1) sele cts the reference source for the adc. for an external source or the on-chip reference, refsl should be set to 0 to select the vref pin. to use v dd as the ref- erence source, refsl should be set to 1. to override this selection and use the internal regulator as the reference source, the rego vr bit can be set to 1. the biase bit enables the internal voltage bias gener ator, which is used by m any of the analog peripher- als on the device. this bias is automatically enabled when any peripheral which r equires it is enabled, and it does not need to be enabled manually. the bias g enerator may be enabled manually by writing a 1 to the biase bit in register ref0cn. the el ectrical specifications for the vo ltage reference circuit are given in table 4.12. the c8051f380/1/2/3 devices also include an on-chip voltage reference circuit wh ich consists of a 1.2 v, temperature stable bandgap voltage reference generator and a selectable-gain output buffer amplifier. the buffer is configured for 1x or 2x gain using the refb gs bit in register ref0cn. on the 1x gain setting the output voltage is nominally 1.2 v, and on the 2x gain setting the output voltage is nominally 2.4 v. the on- chip voltage reference can be driven on the vref pin by setting the refbe bit in register ref0cn to a 1. the maximum load seen by the vref pin must be le ss than 200 a to gnd. bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to g nd, and a minimum of 0.1uf is required. if the on- chip reference is not used, the refbe bit should be cleared to 0. electrical specifications for the on-chip voltage reference are given in table 4.12. important note about the vref pin: when using either an external vo ltage reference or the on-chip ref- erence circuitry, the vref pin should be configured as an analog pin and skipped by the digital crossbar. refer to section ?19. port input/output? on page 150 for the location of the vref pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. figure 6.1. voltage reference functional block diagram to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en bias generator to adc, idac, internal oscillators, reference, tempsensor en ioscen 0 1 ref0cn refsl tempe biase refbe regovr refbgs refbe recommended bypass capacitors + 4.7 ? f0.1 ? f vref (to adc) 0 1 internal regulator regovr 1.2v reference en 1x/2x refbgs
c8051f380/1/2/3/4/5/6/7 58 rev. 1.0 sfr address = 0xd1; sfr page = all pages sfr definition 6.1. ref0cn: reference control bit76543210 name refbgs regovr refsl tempe biase refbe type r/w r r r/w r/w r/w r/w r/w reset 00000000 bit name function 7 refbgs reference buffer gain select. this bit selects between 1x and 2x gain for the on-chip voltage reference buffer. 0: 2x gain 1: 1x gain 6:5 unused read = 00b; write = don?t care. 4regovr regulator reference override. this bit ?overrides? the refsl bit, and allows the internal regulator to be used as a ref- erence source. 0: the voltage reference source is selected by the refsl bit. 1: the internal regulator is used as the voltage reference. 3 refsl voltage reference select. this bit selects the adcs voltage reference. 0: v ref pin used as voltage reference. 1: v dd used as voltage reference. 2 tempe temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 refbe on-chip reference buffer enable bit. 0: on-chip reference buffer off. 1: on-chip reference buffer on. internal voltage reference driven on the v ref pin.
rev. 1.0 59 c8051f380/1/2/3/4/5/6/7 7. comparator0 and comparator1 c8051f380/1/2/3/4/5/6/7 de vices include two on-chip programmable voltage comparators: comparator0 is shown in figure 7.1, comparator1 is shown in figure 7.2. the two comparators operate identically with the following exceptions: (1) their inpu t selections differ as described in section ?7.1. comparator multiplex- ers? on page 66; (2) comparator0 can be used as a reset source. the comparators offer programmable response time and hysteresis, an analog in put multiplexer, and two outputs that are optionally available at the port pins : a synchronous ?latched? output (cp0 or cp1), or an asynchronous ?raw? output (cp0a or cp1a). the asyn chronous signals are available even when the sys- tem clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outputs may be configured as open drain or push-pull (see section ?19.2. port i/o initialization? on page 155). comparator0 may also be used as a reset source (see section ?16.5. comparator0 reset? on page 129). the comparator inputs are selected by the compar ator input multiplexers, as detailed in section ?7.1. comparator multiplexers? on page 66. figure 7.1. comparator0 functional block diagram vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0
c8051f380/1/2/3/4/5/6/7 60 rev. 1.0 figure 7.2. comparator1 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the co mparator output is available asyn chronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the compar ator is turned off. see section ?19.1. priority crossbar decoder? on page 151 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in section ?4. electrical characteristics? on page 34. the comparator response time may be configured in software via the cptnmd registers (see sfr defini- tion 7.2 and sfr definition 7.4). selecting a longer re sponse time reduces the comparator supply current. vdd + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp1 + cp1 - cpt1md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 interrupt 0 1 0 1 cp1rif cp1fif 0 1 cp1en 0 1 ea comparator input mux cpt1cn cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0
rev. 1.0 61 c8051f380/1/2/3/4/5/6/7 figure 7.3. comparator hysteresis plot the comparator hysteresis is software-programm able via its comparator control register cptncn (for n = 0 or 1). the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator hysteresis is programmed using bits 3 ? 0 in the comparator control register cptncn (shown in sfr definition 7.1). the amount of negativ e hysteresis voltage is determined by the settings of the cpnhyn bits. settings of 20, 10 or 5 mv of nomi nal negative hysteresis can be programmed, or nega- tive hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cpnhyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see section ?15.1. mcu interrupt sour ces and vectors? on page 116). the cpnfif flag is set to logic 1 upon a comparator falling-edge occurrence, and the cpnrif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft- ware. the comparator rising-edge interrupt mask is enabled by setting cpnrie to a logic 1. the compar- ator falling-edge interrupt mask is e nabled by setting cpnfie to a logic 1. the output state of the comparator can be obtained at any time by reading the cpnout bit. the compar- ator is enabled by setting the cpnen bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is first powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. positive hysteresis voltage (programmed with cpnhyp bits) negative hysteresis voltage (programmed by cpnhyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
c8051f380/1/2/3/4/5/6/7 62 rev. 1.0 sfr address = 0x9b; sfr page = all pages sfr definition 7.1. cpt0cn : comparator0 control bit76543210 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
rev. 1.0 63 c8051f380/1/2/3/4/5/6/7 sfr address = 0x9d; sfr page = all pages sfr definition 7.2. cpt0md: co mparator0 mode selection bit76543210 name cp0rie cp0fie cp0md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused read = 00b, write = don?t care. 5cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f380/1/2/3/4/5/6/7 64 rev. 1.0 sfr address = 0x9a; sfr page = all pages sfr definition 7.3. cpt1cn : comparator1 control bit76543210 name cp1en cp1out cp1rif cp1fif cp1hyp[1:0] cp1hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp1en comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. 6cp1out comparator1 output state flag. 0: voltage on cp1+ < cp1 ? . 1: voltage on cp1+ > cp1 ? . 5cp1rif comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occurred since this flag was last cleared. 1: comparator1 rising edge has occurred. 4cp1fif comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-edge has occu rred since this flag was last cleared. 1: comparator1 falling- edge has occurred. 3:2 cp1hyp[1:0] comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp1hyn[1:0] comparator1 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv.
rev. 1.0 65 c8051f380/1/2/3/4/5/6/7 sfr address = 0x9c; sfr page = all pages sfr definition 7.4. cpt1md: co mparator1 mode selection bit76543210 name cp1rie cp1fie cp1md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused read = 00b, write = don?t care. 5cp1rie comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. 4cp1fie comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge inte rrupt disabled. 1: comparator1 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp1md[1:0] comparator1 mode select. these bits affect the response time and power consumption for comparator1. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f380/1/2/3/4/5/6/7 66 rev. 1.0 7.1. comparator multiplexers c8051f380/1/2/3/4/5/6/7 devices include an analog inpu t multiplexer to connect port i/o pins to the com- parator inputs. the comparator inputs are selected in the cptnmx registers (sfr definition 7.5 and sfr definition 7.6). the cmxnp2 ? cmxnp0 bits select the comparator positive input; the cmxnn2 ? cmxnn0 bits select the comparator negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar (for details on port configuration, see section ?19.3. general purpose port i/o? on page 158). figure 7.4. comparator input multiplexer block diagram + - cp1 + cp1 - gnd vdd + - cp0 + cp0 - gnd vdd cpt0mx cmx0n2 cmx0n1 cmx0n0 cmx0p2 cmx0p1 cmx0p0 cpt1mx cmx1n2 cmx1n1 cmx1n0 cmx1p2 cmx1p1 cmx1p0
rev. 1.0 67 c8051f380/1/2/3/4/5/6/7 sfr address = 0x9f; sfr page = all pages sfr definition 7.5. cpt0mx: comparator0 mux selection bit76543210 name cmx0n[2:0] cmx0p[2:0] type rr/wrr/w reset 00000000 bit name function 7 unused read = 0b; write = don?t care. 6:4 cmx0n[2:0] comparator0 negative input mux selection. selection 32-pin package 48-pin package 000: p1.1 p2.1 001: p1.5 p2.6 010: p2.1 p3.5 011: p2.5 p4.4 100: p0.1 p0.4 101-111: reserved reserved 3 unused read = 0b; write = don?t care. 2:0 cmx0p[2:0] comparator0 positive input mux selection. selection 32-pin package 48-pin package 000: p1.0 p2.0 001: p1.4 p2.5 010: p2.0 p3.4 011: p2.4 p4.3 100: p0.0 p0.3 101-111: reserved reserved
c8051f380/1/2/3/4/5/6/7 68 rev. 1.0 sfr address = 0x9e; sfr page = all pages sfr definition 7.6. cpt1mx: comparator1 mux selection bit76543210 name cmx1n[2:0] cmx1p[2:0] type rr/wrr/w reset 00000000 bit name function 7 unused read = 0b; write = don?t care. 6:4 cmx1n[2:0] comparator1 negative input mux selection. selection 32-pin package 48-pin package 000: p1.3 p2.3 001: p1.7 p3.1 010: p2.3 p4.0 011: reserved p4.6 100: p0.5 p1.2 101-111: reserved reserved 3 unused read = 0b; write = don?t care. 2:0 cmx1p[2:0] comparator1 positive input mux selection. selection 32-pin package 48-pin package 000: p1.2 p2.2 001: p1.6 p3.0 010: p2.2 p3.7 011: reserved p4.5 100: p0.4 p1.1 101-111: reserved reserved
rev. 1.0 69 c8051f380/1/2/3/4/5/6/7 8. voltage regulato rs (reg0 and reg1) c8051f380/1/2/3/4/5/6/7 devices include two internal voltage regulators: one regulates a voltage source on regin to 3.3 v (reg0), and the other regulate s the internal core supply to 1.8 v from a v dd supply of 1.8 to 3.6 v (reg1). when enabled, the reg0 output appears on the v dd pin and can be used to power external devices. reg0 can be enabled/disabled by software using bit reg0dis in register reg01cn (sfr definition 8.1). reg1 has two power-saving modes built into the regulator to help reduce current consumption in low- power applications. these modes are access ed through the reg01cn register. elec- trical characteristics for the on-chip regulators are specified in table 4.5 on page 37. note that the vbus signal must be connected to th e vbus pin when using the device in a usb network. the vbus signal should only be connected to the re gin pin when operating t he device as a bus-powered function. reg0 configuration options are shown in figure 8.1?figure 8.4. 8.1. voltage regulator (reg0) 8.1.1. regulator mode selection reg0 offers a low power mode intended for use when the device is in suspend mode. in this low power mode, the reg0 output remains as specified; however the reg0 dyna mic performance (response time) is degraded. see table 4.5 for normal and low power mode supply current specif ications. the reg0 mode selection is controlled via the re g0md bit in register reg01cn. 8.1.2. vbus detection when the usb function controller is used (see se ction section ?20. universa l serial bus controller (usb0)? on page 169), the vbus signa l should be conn ected to the vbus pin. the vbstat bit (register reg01cn) indicates the current logic level of the vbu s signal. if enabled, a vbus interrupt will be gener- ated when the vbus signal has eith er a falling or rising edge. the vbu s interrupt is edg e-sensitive, and has no associated interrupt pending flag. see table 4.5 for vbus input parameters. important note: when usb is selected as a re set source, a system reset w ill be generated when a falling or rising edge occurs on the vbus pin. see section ?16. reset sources? on page 126 for details on select- ing usb as a reset source. figure 8.1. reg0 configuration: usb bus-powered voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus from vbus to 3 v power net device power net vdd
c8051f380/1/2/3/4/5/6/7 70 rev. 1.0 figure 8.2. reg0 configuration: usb self-powered figure 8.3. reg0 configuration: usb self-powered, regulator disabled voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net from vbus voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus from 3 v power net device power net vdd from vbus
rev. 1.0 71 c8051f380/1/2/3/4/5/6/7 figure 8.4. reg0 configuration: no usb connection voltage regulator (reg0) 5 v in 3 v out vbus sense regin vbus to 3 v power net device power net vdd from 5 v power net
c8051f380/1/2/3/4/5/6/7 72 rev. 1.0 8.2. voltage regulator (reg1) under default conditions, th e internal reg1 regulator will remain on when the device enters stop mode. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the inter- nal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin and a full power cycle of the device are the only methods of generating a reset. reg1 offers an additional low power mode intended fo r use when the device is in suspend mode. this low power mode should not be used during normal operation or if the reg0 voltage regulator is disabled. see table 4.5 for normal and low power mode supply current specifications. th e reg1 mode selection is controlled via the reg1md bit in register reg01cn. important note: at least 12 clock instructions must occur after placing reg1 in low power mode before the internal high frequ ency oscillator is susp ended (oscicn.5 = 1b).
rev. 1.0 73 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc9; sfr page = all pages sfr definition 8.1. reg01cn: voltage regulator control bit76543210 name reg0dis vbstat reserved reg0md stopcf reserved reg1md reserved type r/w r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7reg0dis voltage regulator (reg0) disable. this bit enables or disables the reg0 voltage regulator. 0: voltage regulator enabled. 1: voltage regulator disabled. 6 vbstat vbus signal status. this bit indicates whether the devi ce is connected to a usb network. 0: vbus signal currently absent (d evice not attached to usb network). 1: vbus signal currently present (device attached to usb network). 5 reserved must write 0b. 4reg0md voltage regulator (reg0) mode select. this bit selects the voltage regulator mode for reg0. when reg0md is set to 1, the reg0 voltage regulator operates in lower power (suspend) mode. 0: reg0 voltage regulator in normal mode. 1: reg0 voltage regula tor in low power mode. 3stopcf stop mode configuration (reg1). this bit configures the reg1 regulator?s behavior when the device enters stop mode. 0: reg1 regulator is still active in stop mode. any enabled rese t source will reset the device. 1: reg1 regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 2 reserved must write 0b. 1reg1md voltage regulator (reg1) mode. this bit selects the voltage regulator mode for reg1. when reg1md is set to 1, the reg1 voltage regulator operates in lower power mode. 0: reg1 voltage regulator in normal mode. 1: reg1 voltage regula tor in low power mode. this bit should not be set to '1' if the reg0 voltage regulator is disabled. 0 reserved must write 0b.
c8051f380/1/2/3/4/5/6/7 74 rev. 1.0 9. power management modes the c8051f380/1/2/3/4/5/ 6/7 devices have three software programmable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while sus- pend mode is an e nhanced power-saving mode implemented by the high-sp eed oscillator peripheral. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator is halt ed, but the device ca n wake on activ- ity with the usb transceiver. the cpu is not halted in suspend mode, so it can r un on another oscillator, if desired. since clocks are running in idle mode, po wer consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 9.1 describes the power control register (pcon) used to c ontrol the c8051f380/1/2/3/4/5/6/7's stop and idle power ma nagement modes. suspend mode is co ntrolled by the suspend bit in the oscicn register (sfr definition 18.3). although the c8051f380/1/2/ 3/4/5/6/7 has idle, stop, and suspend mo des available, more control over the device power can be achieved by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as tim- ers or serial buses, draw little powe r when they are not in use. turnin g off oscillators lowers power con- sumption considerably, at the expense of reduced functionality. 9.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction imme diately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instructio n following the write of the idle bit is a si ngle-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructi ons that set the idle bit should be followed by an instruction that has two or mo re opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi-
rev. 1.0 75 c8051f380/1/2/3/4/5/6/7 nitely, waiting for an external stim ulus to wake up the system. refer to section ?16.6. pca watchdog timer reset? on page 130 for more information on the use a nd configuration of the wdt. 9.2. stop mode setting the stop mode select bit (pco n.1) causes the controller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. ea ch analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detector will cause an inte rnal reset and thereby te rminate the stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. by default, when in stop mode the internal regulator is still active. ho wever, the regulator can be config- ured to shut down while in stop mode to save pow er. to shut down the regulator in stop mode, the stopcf bit in register reg01cn should be set to 1 prior to setting the stop bit (see sfr definition 8.1). if the regulator is shut down using the stopcf bit, only the rst pin or a full power cycle are capable of resetting the device. 9.3. suspend mode setting the suspend bit (oscicn.5) causes the hardwa re to halt the high-frequency in ternal oscillator and go into suspend mode as soon as the instruction t hat sets the bit completes execution. all internal reg- isters and memory maintain their or iginal data. the cpu is not halted in suspend, so code can still be exe- cuted using an oscillator other than the in ternal high-frequency oscillator. suspend mode can be term inated by resume signa lling on the usb data pins, or a device reset event. when suspend mode is term inated, if the oscillator so urce is the internal high -frequency oscillator, the device will continue execut ion on the instruction following the one that set the suspend bit. if the wake event was configured to generate an interrupt, the interrupt will be serv iced upon waking t he device. if sus- pend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000.
c8051f380/1/2/3/4/5/6/7 76 rev. 1.0 sfr address = 0x87; sfr page = all pages sfr definition 9.1. pcon: power control bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip-51 in stop mode. this bit will always be read as 0. 1: cpu goes into stop mode (i nternal oscillator stopped). 0idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.)
rev. 1.0 77 c8051f380/1/2/3/4/5/6/7 10. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see descriptio n in section 27), and interfaces directly with the ana- log and digital subsystems providing a complete data acqu isition or control-system so lution in a single inte- grated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 10.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except fo r mul and div take 12 or 24 system clock cycles to execute, and usually have a maximu m system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 10.1. cip-51 block diagram ? fully compatible with mc s-51 instruction set ? 48 mips peak throughput with 48 mhz clock ? 0 to 48 mhz clock frequency ? extended interrupt handler ? reset input ? power management modes ? on-chip debug logic ? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
c8051f380/1/2/3/4/5/6/7 78 rev. 1.0 with the cip-51's maximum system clock at 48 mhz, it has a peak throughput of 48 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem- ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or other on-chip resources. c2 details can be found in section ?27. c2 interface? on page 313. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro- vides an integrated development environment (ide) in cluding editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-sys- tem device programming and debugging. third party macro assemblers and c compilers are also avail- able. 10.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 10.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction ti mings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as o pposed to when the branch is taken. table 10.1 is the cip-51 instruction set summary, which includes the mnemonic, number of byte s, and number of clock cycles for each instruction. clocks to execute 1 2 2/4 3 3/5 4 5 4/6 6 8 number of instructions 2650510652221
rev. 1.0 79 c8051f380/1/2/3/4/5/6/7 table 10.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2
c8051f380/1/2/3/4/5/6/7 80 rev. 1.0 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 table 10.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
rev. 1.0 81 c8051f380/1/2/3/4/5/6/7 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 program flow timings are listed with the pfe on and flrt = 0. ex tra cycles are required for branches if flrt = 1. jc rel jump if carry is set 2 2/4 jnc rel jump if carry is not set 2 2/4 jb bit, rel jump if direct bit is set 3 3/5 jnb bit, rel jump if direct bit is not set 3 3/5 jbc bit, rel jump if direct bit is set and clear bit 3 3/5 acall addr11 absolute subroutine call 2 4 lcall addr16 long subroutine call 3 5 ret return from subroutine 1 6 reti return from interrupt 1 6 ajmp addr11 absolute jump 2 4 ljmp addr16 long jump 3 5 sjmp rel short jump (relative address) 2 4 jmp @a+dptr jump indirect relative to dptr 1 4 jz rel jump if a equals zero 2 2/4 jnz rel jump if a does not equal zero 2 2/4 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/6 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/5 cjne rn, #data, rel compare immediate to register and jump if not equal 33/5 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/6 djnz rn, rel decrement regist er and jump if not zero 2 2/4 djnz direct, rel decrement direct byte and jump if not zero 3 3/5 nop no operation 1 1 table 10.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
c8051f380/1/2/3/4/5/6/7 82 rev. 1.0 notes on registers, operands and addressing modes: rn - register r0?r7 of the curr ently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.0 83 c8051f380/1/2/3/4/5/6/7 10.2. cip-51 re gister descriptions following are descriptions of sfrs related to the opera tion of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implem ent new features in which ca se the reset value of the bi t will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the datasheet associated with their corresponding system function. sfr address = 0x82; sfr page = all pages sfr address = 0x83; sfr page = all pages sfr definition 10.1. dpl: data pointer low byte bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 10.2. dph: data pointer high byte bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr.
c8051f380/1/2/3/4/5/6/7 84 rev. 1.0 sfr address = 0x81; sfr page = all pages sfr address = 0xe0; sfr page = all pages; bit-addressable sfr address = 0xf0; sfr page = all pages; bit-addressable sfr definition 10.3. sp: stack pointer bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre- mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 10.4. acc: accumulator bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 10.5. b: b register bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations.
rev. 1.0 85 c8051f380/1/2/3/4/5/6/7 sfr address = 0xd0; sfr page = all pages; bit-addressable sfr definition 10.6. psw: program status word bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor- row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith- metic operations. 5f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: ?? an add, addc, or subb instruction causes a sign-change overflow. ?? a mul instruction results in an overflow (result is greater than 255). ?? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even.
c8051f380/1/2/3/4/5/6/7 86 rev. 1.0 11. prefetch engine the c8051f380/1/2/3/4/5/6/7 family of devices incorporate a 2-byte prefetch engine. because the access time of the flash memory is 40 ns, and the minimum in struction time is roughly 20 ns, the prefetch engine is necessary for full-speed code exec ution. instructions are read from fl ash memory two bytes at a time by the prefetch engine and given to the cip-51 processor core to execute. when running linear code (code without any jumps or branches), the prefetch engine allo ws instructions to be executed at full speed. when a code branch occurs, the processor may be stalled fo r up to two clock cycles while the next set of code bytes is retrieved from flash memory. it is recommended that the prefetch be used for optimal code execu- tion timing. note: the prefetch engine can be disabled when the device is in suspend mode to save power. sfr address = 0xaf; sfr page = all pages sfr definition 11.1. pfe0cn: prefetch engine control bit76543210 name pfen flbwe type rrr/wrrrrr/w reset 00100000 bit name function 7:6 unused read = 00b, write = don?t care. 5pfen prefetch enable. this bit enables the prefetch engine. 0: prefetch engine is disabled. 1: prefetch engine is enabled. 4:1 unused read = 0000b. write = don?t care. 0flbwe flash block write enable. this bit allows block writes to flash memory from software. 0: each byte of a software flash write is written individually. 1: flash bytes are written in groups of two.
rev. 1.0 87 c8051f380/1/2/3/4/5/6/7 12. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different in struction types. the cip- 51 memory organization is shown in figure 12.1 and figure 12.2. figure 12.1. on-chip memory map for 64 kb devices (c8051f380/1/4/5) program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram (available only on devices with emif) 0x0400 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0xfc00 0xfbff usb fifos 1024 bytes 0x07ff 0x1000 0xffff
c8051f380/1/2/3/4/5/6/7 88 rev. 1.0 figure 12.2. on-chip memory map for 32 kb devices (c8051f382/3/6/7) 12.0.1. program memory the cip-51 core has a 64k-byte program memory space. the c8051f380/1/2/3/4/5/6/7 implements 64 or 32 kb of this program memory space as in-system, re-programmable flash memory. note that on the c8051f380/1/4/5 (64 kb version), addresses above 0xfbff are reserved. program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl .0) and using the movx instruction. this feature provides a mechanism for the cip-51 to update pr ogram code and use the program memory space for non-volatile data storage. refer to section ?17. flash memory? on page 132 for further details. 12.0.2. data memory the cip-51 includes 256 of internal ram mapped in to the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locati ons 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 2048 bytes (accessable using movx instruction) 0x0000 0x07ff off-chip xram (available only on devices with emif) 0x0400 0xffff flash (in-system programmable in 512 byte sectors) 0x0000 0x7fff usb fifos 1024 bytes 0x07ff 0x0800
rev. 1.0 89 c8051f380/1/2/3/4/5/6/7 space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory . figure 12.1 illustrates the data me mory organizatio n of the cip-51. 12.0.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of ei ght byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see desc ription of the psw in sfr definition 10.6). this allows fast context switching when entering subroutines and in terrupt service routines. in direct addressing modes use registers r0 and r1 as index registers. 12.0.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22h.3 moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 12.0.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp+1 and then sp is incremented. a reset init ializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
c8051f380/1/2/3/4/5/6/7 90 rev. 1.0 13. external data memory interface and on-chip xram 4 kb (c8051f380/1/4/5) or 2 kb (c8051f382/3/6/7) of ram are included on-chip, and mapped into the external data memory space (xram). the 1 kb of usb fifo space can also be mapped into xram address space for additional general-purpose data stor age. additionally, an external memory interface (emif) is available on the c8051f380/2/4/6 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the gpio po rts. the external memory space may be accessed using the external move instruction (movx) and the data pointer (dptr), or using the movx indirect addressing mode using r0 or r1. if the movx inst ruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is pr ovided by the external memory interface control reg- ister (emi0cn, shown in sfr definition 13.1). note: the movx instruction can also be used for writing to the flash memory. see section ?17. flash memory ? on page 132 for details. the movx instruction accesses xram by default. 13.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec- ond method uses r0 or r1 in combination with th e emi0cn register to generate the effective xram address. examples of both of these methods are given below. 13.1.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location pointed to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a the above example uses the 16-bit immediate mov in struction to set the contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 13.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the contents of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the co ntents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following seri es of instructions read t he contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a
rev. 1.0 91 c8051f380/1/2/3/4/5/6/7 13.2. accessing usb fifo space the c8051f380/1/2/3/4/5/6/7 include 1k of ram whic h functions as usb fifo space. figure 13.1 shows an expanded view of the fifo space and user xr am. fifo space is norma lly accessed via usb fifo registers; see section ?20.5. fifo management? on page 178 for more information on accessing these fifos. the movx instruction should not be used to load or modify usb data in the fifo space. unused areas of the usb fifo space may be used as general purpose xram if necessary. the fifo block operates on the usb clock dom ain; thus the usb clock must be active when accessing fifo space. note that the number of sysclk cycles required by the movx instruction is increased when accessing usb fifo space. to access the fifo ram directly using movx instructio ns, the following conditions must be met: (1) the usbfae bit in register emi0cf must be set to 1, and (2) the usb clock must be greater than or equal to twice the sysclk (usbclk > 2 x sysclk). when this bit is set, the usb fifo spac e is mapped into xram space at addresses 0x0400 to 0x07ff. the normal xram (on-chip or external) at the same addresses cannot be accessed when the usbfae bit is set to 1. important note : the usb clock must be active when accessing fifo space. figure 13.1. usb fifo space and xram memory map with usbfae set to ?1? on/off-chip xram 0x0000 endpoint0 (64 bytes) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes) usb fifo space (usb clock domain) 0x03ff on/off-chip xram 0x0800 0xffff
c8051f380/1/2/3/4/5/6/7 92 rev. 1.0 13.3. configuring the ex ternal memory interface configuring the external memory interface consists of five steps: 1. configure the output modes of the associated port pi ns as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. configure port latches to ?park? the emif pins in a dormant state (usually by setting them to logic 1). 3. select multiplexed mode or non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. each of these five steps is explained in detail in the following sections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition 13.5. 13.4. port configuration the external memory interface appears on ports 4, 3, 2, and 1 when it is used for off-chip memory access. when the emif is used, the crossbar should be conf igured to skip over th e control lines p1.7 (wr ), p1.6 (rd ), and if multiplexed mode is se lected p1.3 (ale) using the p1skip register. for more information about configuring the crossbar, see section ?figure 19.1. port i/o functional block diagram (port 0 through port 3)? on page 150. the external memory interface claims the associated port pins for memory oper ations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches or to the crossbar settings for those pins. see section ?19. port input/out- put? on page 150 for more information about the cr ossbar and port operation and configuration. the port latches should be explicitly configured to ?park? the external memory interface pins in a dormant state, most commonly by setting them to a logic 1 . during the execution of the movx inst ruction, the external memory interf ace will explicitly disable the driv- ers on all port pins that are acting as inputs (dat a[7:0] during a read operati on, for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the external memory interface operation, and remains c ontrolled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode.
rev. 1.0 93 c8051f380/1/2/3/4/5/6/7 sfr address = 0xaa; sfr page = all pages sfr definition 13.1. emi0cn: exte rnal memory interface control bit7654321 0 name pgsel[7:0] type r/w reset 0000000 0 bit name function 7:0 pgsel[7:0] xram page select bits. the xram page select bits provide the hi gh byte of the 16-bit external data mem- ory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff
c8051f380/1/2/3/4/5/6/7 94 rev. 1.0 sfr address = 0x85; sfr page = all pages sfr definition 13.2. emi0cf: extern al memory interf ace configuration bit7654321 0 name usbfae emd2 emd[1:0] eale[1:0] type rr/wrr/w r/w r/w reset 0000001 1 bit name function 7 unused read = 0b; write = don?t care. 6 usbfae usb fifo access enable. 0: usb fifo ram not availabl e through movx instructions. 1: usb fifo ram available using movx in structions. the 1k of usb ram will be mapped in xram space at addresses 0x0400 to 0x07ff. the usb clock must be active and greater than or equa l to twice the sysclk (usbclk > 2 x sys- clk) to access this area with movx instructions. 5 unused read = 0b; write = don?t care. 4emd2 emif multiplex mode select. 0: emif operates in multiplexed address/data mode. 1: emif operates in non-multiplexed mode (separate address and data pins). 3:2 emd[1:0] emif operating mode select. these bits control the operating mode of the external memory interface. 00: internal only: movx accesses on-chi p xram only. all effective addresses alias to on-chip memory space. 01: split mode without bank select: accesses below the on-chip xram boundary are directed on-chip. accesses above the on-chip xram boundary are directed off-chip. 8-bit off-chip movx operations use the current contents of the address high port latches to resolve upper address byte. note that in order to access off-chip space, emi0cn must be set to a page that is not contained in the on-chip address space. 10: split mode with bank select: accesses below the on-chip xram boundary are directed on-chip. accesses above the on-chip xram boundary are directed off-chip. 8-bit off-chip movx operations use the contents of emi0cn to determine the high-byte of the address. 11: external only: movx acce sses off-chip xram only. on-chip xram is not visi- ble to the cpu. 1:0 eale[1:0] ale pulse-width select bits (only has effect when emd2 = 0). 00: ale high and ale low pulse width = 1 sysclk cycle. 01: ale high and ale low pulse width = 2 sysclk cycles. 10: ale high and ale low pulse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles.
rev. 1.0 95 c8051f380/1/2/3/4/5/6/7 13.5. multiplexed and n on-multiplexed selection the external memory interface is capable of acting in a multiplexe d mode or a non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 13.5.1. mult iplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode , an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlle d by the ale (address latch enable) signal, which is driven by the external memory interface logic. an example of a multiplexed configuration is shown in figure 13.2. in multiplexed mode, the external movx operation can be broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are pre- sented to ad[7:0]. during this phase , the address latch is configured such that the ?q? outputs reflect the states of the ?d? inputs. when ale falls, signaling th e beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of the ad[7:0] port at the time rd or wr is asserted. see section ?13.7.2. multiplexed mode? on page 104 for more information. figure 13.2. multiplexed configuration example 13.5.2. non-multiple xed configuration in non-multiplexed mode, the data bus and the address bus pins are not shared. an example of a non-multiplexed configuration is shown in figure 13.3. see section ?13.7.1. non-multiplexed mode? on page 101 for more information about non-multiplexed operation. address/data bus address bus e m i f a[15:8] ad[7:0] wr rd ale 64k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional)
c8051f380/1/2/3/4/5/6/7 96 rev. 1.0 figure 13.3. non-multiplexed configuration example address bus e m i f a[15:0] 64k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 wr rd oe we ce (optional)
rev. 1.0 97 c8051f380/1/2/3/4/5/6/7 13.6. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 13.4, based on the emif mode bits in the emi0cf register (sfr definition 13.5). these modes are summarized below. more information about the different modes can be found in section ?13.7. timing? on page 99. figure 13.4. emif operating modes 13.6.1. intern al xram only when emi0cf.[3:2] are set to 00, all movx instructions will target t he internal xram sp ace on the device. memory accesses to addresses beyo nd the populated space will wrap on 2k or 4k bound aries (depending on the ram available on the device). as an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16-bit dptr to determine the effective address. 13.6.2. split mode without bank select when emi0cf.[3:2] are set to 01, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. however, in the ?no bank se lect? mode, an 8-bit movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory
c8051f380/1/2/3/4/5/6/7 98 rev. 1.0 13.6.3. split mode with bank select when emi0cf.[3:2] are set to 10, the xram memory map is split into two areas, on-chip space and off-chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on-chip or off-chip. the upper 8-bits of the addr ess bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 13.6.4. external only when emi0cf[3:2] are set to 11, all movx operations ar e directed to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for accessing off-chip memo ry located between 0x0000 and the internal xram size boundary. ? 8-bit movx operations ignore the contents of emi0 cn. the upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the up per address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction.
rev. 1.0 99 c8051f380/1/2/3/4/5/6/7 13.7. timing the timing parameters of the external memory in terface can be configured to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, rd and wr strobe widths, and in multip lexed mode, the width of the ale pulse are all programmable in units of sysclk periods throug h emi0tc, shown in sfr defini tion 13.3, and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculated by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assumi ng non-multiplexed operation, the minimum execution time for an off-chip xram operatio n is 5 sysclk cycles (1 sysclk for rd or wr pulse + 4 sysclks). for multiplexed operations , the address latch enable signal will re quire a minimum of 2 additional sys- clk cycles. therefore, the minimum ex ecution time for an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 for ale + 1 for rd or wr + 4). the programmable setup and hold times default to the maximum delay settings after a reset. table 13.1 lists the ac parameters for the external memory inter- face, and figure 13.5 through figure 13.10 show the timing diagrams for the different external memory interface modes and movx operations.
c8051f380/1/2/3/4/5/6/7 100 rev. 1.0 sfr address = 0x84; sfr page = all pages sfr definition 13.3. emi0tc: ex ternal memory timing control bit7654321 0 name eas[1:0] ewr[3:0] eah[1:0] type r/w r/w r/w reset 1111111 1 bit name function 7:6 eas[1:0] emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. 5:2 ewr[3:0] emif wr and rd pulse-width control bits. 0000: wr and rd pulse width = 1 sysclk cycle. 0001: wr and rd pulse width = 2 sysclk cycles. 0010: wr and rd pulse width = 3 sysclk cycles. 0011: wr and rd pulse width = 4 sysclk cycles. 0100: wr and rd pulse width = 5 sysclk cycles. 0101: wr and rd pulse width = 6 sysclk cycles. 0110: wr and rd pulse width = 7 sysclk cycles. 0111: wr and rd pulse width = 8 sysclk cycles. 1000: wr and rd pulse width = 9 sysclk cycles. 1001: wr and rd pulse width = 10 sysclk cycles. 1010: wr and rd pulse width = 11 sysclk cycles. 1011: wr and rd pulse width = 12 sysclk cycles. 1100: wr and rd pulse width = 13 sysclk cycles. 1101: wr and rd pulse width = 14 sysclk cycles. 1110: wr and rd pulse width = 15 sysclk cycles. 1111: wr and rd pulse width = 16 sysclk cycles. 1:0 eah[1:0] emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles.
rev. 1.0 101 c8051f380/1/2/3/4/5/6/7 13.7.1. non-multiplexed mode 13.7.1.1. 16-bit movx: emi0 cf[4:2] = 101, 110, or 111 figure 13.5. non-multiplexed 16-bit movx timing emif address (8 msbs) from dph emif address (8 lsbs) from dpl p3 p2 p1.7 p1.6 p4 emif write data p3 p2 p1.7 p1.6 p4 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl p3 p2 p1.6 p1.7 p4 p3 p2 p1.6 p1.7 p4 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read
c8051f380/1/2/3/4/5/6/7 102 rev. 1.0 13.7.1.2. 8-bit movx without bank select: emi0cf[4:2] = 101 or 111 figure 13.6. non-multiplexed 8-bit movx without bank select timing emif address (8 lsbs) from r0 or r1 p3 p2 p1.7 p1.6 p4 emif write data p3 p1.7 p1.6 p4 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 lsbs) from r0 or r1 p3 p2 p1.6 p1.7 p4 p3 p1.6 p1.7 p4 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select
rev. 1.0 103 c8051f380/1/2/3/4/5/6/7 13.7.1.3. 8-bit mo vx with bank select: emi0cf[4:2] = 110 figure 13.7. non-multiplexed 8-bit movx with bank select timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select
c8051f380/1/2/3/4/5/6/7 104 rev. 1.0 13.7.2. mult iplexed mode 13.7.2.1. 16-bit movx: emi0 cf[4:2] = 001, 010, or 011 figure 13.8. multiplexed 16-bit movx timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read
rev. 1.0 105 c8051f380/1/2/3/4/5/6/7 13.7.2.2. 8-bit movx without bank select: emi0cf[4:2] = 001 or 011 figure 13.9. multiplexed 8-bit movx without bank select timing p4 p3 p4 addr[15:8] ad[7:0] p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select
c8051f380/1/2/3/4/5/6/7 106 rev. 1.0 13.7.2.3. 8-bit mo vx with bank select: emi0cf[4:2] = 010 figure 13.10. multiplexed 8-bit movx with bank select timing p4 p3 p4 addr[15:8] ad[7:0] p3 p1.7 p1.6 p1.3 p1.7 p1.6 p1.3 t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p4 p3 p4 addr[15:8] ad[7:0] p3 p1.6 p1.7 p1.3 p1.6 p1.7 p1.3 t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select
rev. 1.0 107 c8051f380/1/2/3/4/5/6/7 table 13.1. ac parameters for external memory interface parameter description min* max* units t acs address/control setup time 0 3 x t sysclk ns t acw address/control pulse width 1 x t sysclk 16 x t sysclk ns t ach address/control hold time 0 3 x t sysclk ns t aleh address latch enable high time 1 x t sysclk 4xt sysclk ns t alel address latch enable low time 1 x t sysclk 4xt sysclk ns t wds write data setup time 1 x t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ns t rdh read data hold time 0 ns note: t sysclk is equal to one period of the device system clock (sysclk).
c8051f380/1/2/3/4/5/6/7 108 rev. 1.0 14. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchange with the c8051f380/1/2/3/4/5/6/7's resources and peripherals. the cip-51 controller core duplicates the sf rs found in a typical 8051 implementation as well as implementing additional sfrs used to configure and access the sub-systems unique to the c8051f380/1/2/3/4/5/6/7. this allows the addition of new functiona lity while retaining compatibility with the mcs-51? instruction set. table 14.1 lists the sfrs implemented in the c8051f380/1/2/3/4/5/6/7 device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all ot her sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserv ed for future use. ac cessing these areas will have an in determinate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in table 14.2, for a detailed description of each register. 14.1. 13.1. sfr paging the cip-51 features sfr paging, allowing the device to map many sfrs into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages. in this way, each memory location from 0x80 to 0xff can access up to 256 sfrs. th e c8051f380/1/2/3/4/5/6/7 devices utilize two sfr pages: 0x0, and 0xf. most sfrs are available on both pages. sfr p ages are selected using the special function register page selection register, sfrpage. the procedure for reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2. use direct accessing mode to read or write t he special function register (mov instruction). important note: when reading or writing sfrs that are not available on all pages within an isr, it is rec- ommended to save the state of the sfrpage register on isr entry, and restore state on exit. sfr address = 0xbf; sfr page = all pages sfr definition 14.1. sfrpage: sfr page bit7654321 0 name sfrpage[7:0] type r/w reset 0000000 0 bit name function 7:0 sfrpage[7:0] sfr page bits. represents the sfr page the c8051 core uses when reading or modifying sfrs. write: sets the sfr page. read: byte is the sfr page the c8051 core is using.
rev. 1.0 109 c8051f380/1/2/3/4/5/6/7 table 14.1. special function register (sfr) memory map address page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin p2mdin p3mdin p4mdin eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 0 acc xbr0 xbr1 xbr2 it01cf smod1 eie1 eie2 fckcon1 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 p3skip d0 psw ref0cn scon1 sbuf1 p0skip p1skip p2skip usb0xcn c8 tmr2cn reg01cn tmr2rll tmr2rlh tmr2l tmr2h smb0adm smb0adr tmr5cn tmr5rll tmr5rlh tmr5l tmr5h smb1adm smb1adr c0 0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth p4 f smb1cn smb1cf smb1dat b8 0 ip clkmul amx0n amx0p adc0cf adc0l adc0h sfrpage f smbtc b0 p3 oscxcn oscicn oscicl sbrll1 sbrlh1 flscl flkey a8 ie clksel emi0cn sbcon1 p4mdout pfe0cn a0 p2 spi0cfg spi0ckr spi0dat p0md out p1mdout p2mdout p3mdout 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 0 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h usb0adr usb0dat f tmr4cn tmr4rll tmr4rlh tmr4l tmr4h 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph emi0tc emi0cf osclcn pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) notes: 1. sfr addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions. 2. unless indicated otherwise, sfrs are available on both page 0 and page f.
c8051f380/1/2/3/4/5/6/7 110 rev. 1.0 table 14.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page acc 0xe0 all pages accumulator 84 adc0cf 0xbc all pages adc0 configuration 48 adc0cn 0xe8 all pages adc0 control 50 adc0gth 0xc4 all pages adc0 greater-than compare high 51 adc0gtl 0xc3 all pages adc0 greater-than compare low 51 adc0h 0xbe all pages adc0 high 49 adc0l 0xbd all pages adc0 low 49 adc0lth 0xc6 all pages adc0 less-than compare word high 52 adc0ltl 0xc5 all pages adc0 less-than compare word low 52 amx0n 0xba all pages amux0 negative channel select 56 amx0p 0xbb all pages amux0 posi tive channel select 55 b 0xf0 all pages b register 84 ckcon 0x8e all pages clock control 261 ckcon1 0xe4 f clock control 1 262 clkmul 0xb9 0 clock multiplier 144 clksel 0xa9 all pages clock select 141 cpt0cn 0x9b all pages comparator0 control 62 cpt0md 0x9d all pages comparato r0 mode selection 63 cpt0mx 0x9f all pages comparato r0 mux selection 67 cpt1cn 0x9a all pages comparator1 control 64 cpt1md 0x9c all pages comparato r1 mode selection 65 cpt1mx 0x9e all pages comparator1 mux selection 68 dph 0x83 all pages data pointer high 83 dpl 0x82 all pages data pointer low 83 eie1 0xe6 all pages extended interrupt enable 1 120 eie2 0xe7 all pages extended interrupt enable 2 122 eip1 0xf6 all pages extended interrupt priority 1 121 eip2 0xf7 all pages extended interrupt priority 2 123 emi0cf 0x85 all pages external memory interface configuration 94 emi0cn 0xaa all pages external memory interface control 93 emi0tc 0x84 all pages external memory interface timing 100 flkey 0xb7 all pages flash lock and key 137 flscl 0xb6 all pages flash scale 138
rev. 1.0 111 c8051f380/1/2/3/4/5/6/7 ie 0xa8 all pages interrupt enable 118 ip 0xb8 all pages interrupt priority 119 it01cf 0xe4 0 int0/int1 configuration 125 oscicl 0xb3 all pages internal o scillator calibration 142 oscicn 0xb2 all pages internal oscillator control 143 osclcn 0x86 all pages internal low-fre quency oscillator control 145 oscxcn 0xb1 all pages external oscillator control 149 p0 0x80 all pages port 0 latch 159 p0mdin 0xf1 all pages port 0 input mode configuration 159 p0mdout 0xa4 all pages port 0 output mode configuration 160 p0skip 0xd4 all pages port 0 skip 160 p1 0x90 all pages port 1 latch 161 p1mdin 0xf2 all pages port 1 input mode configuration 161 p1mdout 0xa5 all pages port 1 output mode configuration 162 p1skip 0xd5 all pages port 1 skip 162 p2 0xa0 all pages port 2 latch 163 p2mdin 0xf3 all pages port 2 input mode configuration 163 p2mdout 0xa6 all pages port 2 output mode configuration 164 p2skip 0xd6 all pages port 2 skip 164 p3 0xb0 all pages port 3 latch 165 p3mdin 0xf4 all pages port 3 input mode configuration 165 p3mdout 0xa7 all pages port 3 output mode configuration 166 p3skip 0xdf all pages port 3skip 166 p4 0xc7 all pages port 4 latch 167 p4mdin 0xf5 all pages port 4 input mode configuration 167 p4mdout 0xae all pages port 4 output mode configuration 168 pca0cn 0xd8 all pages pca control 308 pca0cph0 0xfc all pages pca capture 0 high 312 pca0cph1 0xea all pages pca capture 1 high 312 pca0cph2 0xec all pages pca capture 2 high 312 pca0cph3 0xee all pages pca capture 3high 312 pca0cph4 0xfe all pages pca capture 4 high 312 pca0cpl0 0xfb all pages pca capture 0 low 312 pca0cpl1 0xe9 all pages pca capture 1 low 312 table 14.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page
c8051f380/1/2/3/4/5/6/7 112 rev. 1.0 pca0cpl2 0xeb all pages pca capture 2 low 312 pca0cpl3 0xed all pages pca capture 3 low 312 pca0cpl4 0xfd all pages pca capture 4 low 312 pca0cpm0 0xda all pages pca module 0 mode register 310 pca0cpm1 0xdb all pages pca module 1 mode register 310 pca0cpm2 0xdc all pages pca module 2 mode register 310 pca0cpm3 0xdd all pages pca module 3 mode register 310 pca0cpm4 0xde all pages pca module 4 mode register 310 pca0h 0xfa all pages pca counter high 311 pca0l 0xf9 all pages pca counter low 311 pca0md 0xd9 all pages pca mode 309 pcon 0x87 all pages power control 76 pfe0cn 0xaf all pages prefetch engine control 86 psctl 0x8f all pages program store r/w control 136 psw 0xd0 all pages program status word 85 ref0cn 0xd1 all pages voltage reference control 58 reg01cn 0xc9 all pages voltage regulator 0 and 1 control 73 rstsrc 0xef all pages reset source configuration/status 131 sbcon1 0xac all pages uart1 baud rate generator control 245 sbrlh1 0xb5 all pages uart1 baud rate generator high 245 sbrll1 0xb4 all pages uart1 baud rate generator low 246 sbuf0 0x99 all pages uart0 data buffer 235 sbuf1 0xd3 all pages uart1 data buffer 244 scon0 0x98 all pages uart0 control 234 scon1 0xd2 all pages uart1 control 242 sfrpage 0xbf all pages sfr page select 108 smb0adm 0xce 0 smbus0 address mask 216 smb0adr 0xcf 0 smbus0 address 215 smb0cf 0xc1 0 smbus0 configuration 208 smb0cn 0xc0 0 smbus0 control 212 smb0dat 0xc2 0 smbus0 data 218 smb1adm 0xce f smbus1 address mask 217 smb1adr 0xcf f smbus1 address 216 smb1cf 0xc1 f smbus1 configuration 208 table 14.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page
rev. 1.0 113 c8051f380/1/2/3/4/5/6/7 smb1cn 0xc0 f smbus1 control 213 smb1dat 0xc2 f smbus1 data 219 smbtc 0xb9 f smbus0/1 timing control 210 smod1 0xe5 all pages uart1 mode 243 sp 0x81 all pages stack pointer 84 spi0cfg 0xa1 all pages spi configuration 254 spi0ckr 0xa2 all pages spi clock rate control 256 spi0cn 0xf8 all pages spi control 255 spi0dat 0xa3 all pages spi data 256 tcon 0x88 all pages timer/counter control 267 th0 0x8c all pages timer/counter 0 high 270 th1 0x8d all pages timer/counter 1 high 270 tl0 0x8a all pages timer/counter 0 low 269 tl1 0x8b all pages timer/counter 1 low 269 tmod 0x89 all pages timer/counter mode 268 tmr2cn 0xc8 0 timer/counter 2 control 275 tmr2h 0xcd 0 timer/counter 2 high 277 tmr2l 0xcc 0 timer/counter 2 low 276 tmr2rlh 0xcb 0 timer/counter 2 reload high 276 tmr2rll 0xca 0 timer/counter 2 reload low 276 tmr3cn 0x91 0 timer/counter 3 control 282 tmr3h 0x95 0 timer/counter 3 high 284 tmr3l 0x94 0 timer/counter 3 low 283 tmr3rlh 0x93 0 timer/counter 3 reload high 283 tmr3rll 0x92 0 timer/counter 3 reload low 283 tmr4cn 0x91 f timer/counter 4 control 287 tmr4h 0x95 f timer/counter 4 high 289 tmr4l 0x94 f timer/counter 4 low 288 tmr4rlh 0x93 f timer/counter 4 reload high 288 tmr4rll 0x92 f timer/counter 4 reload low 288 tmr5cn 0xc8 f timer/counter 5 control 292 tmr5h 0xcd f timer/counter 5 high 294 tmr5l 0xcc f timer/counter 5 low 293 tmr5rlh 0xcb f timer/counter 5 reload high 293 table 14.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page
c8051f380/1/2/3/4/5/6/7 114 rev. 1.0 tmr5rll 0xca f timer/counter 5 reload low 293 usb0adr 0x96 all pages usb0 indirect address register 173 usb0dat 0x97 all pages usb0 data register 174 usb0xcn 0xd7 all pages usb0 transceiver control 171 vdm0cn 0xff all pages v dd monitor control 129 xbr0 0xe1 all pages port i/o crossbar control 0 156 xbr1 0xe2 all pages port i/o crossbar control 1 157 xbr2 0xe3 all pages port i/o crossbar control 2 158 table 14.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page
rev. 1.0 115 c8051f380/1/2/3/4/5/6/7 15. interrupts the c8051f380/1/2/3/4/5/6/7 include an extended interrupt system supporting multiple interrupt sources with two priority levels. the alloca tion of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associ- ated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid inter- rupt condition, the associated interr upt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt re quest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (t he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie, eie1, or ei e2). however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears a bit to disable an interrupt should be immediately followed by an instruc- tion that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': ea = 0; // clear ea bit. ea = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: clr ea ; clear ea bit. clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc- tion, the interrupt may be taken. howeve r, a read of the enable bit will retu rn a 0 inside the interrupt service routine. when the bit-cleari ng opcode is followed by a mu lti-cycle instruction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interrup t request will be gener ated immediately and the cpu will re-enter the isr after the completion of the next instruction.
c8051f380/1/2/3/4/5/6/7 116 rev. 1.0 15.1. mcu interrupt sources and vectors the c8051f380/1/2/3/4/5/6/7 mcus support several interrupt sources. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and the cpu w ill vector to the isr addr ess associated with the in terrupt-pending flag. mcu interrupt sources, associated ve ctor addresses, priority order and control bits are summarized in table 15.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 15.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels : low or high. a low prior- ity interrupt service routine can be preempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (i p, eip1, or eip2) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed prior- ity order is used to arbitrate, given in table 15.1. 15.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fastest possible response time is 6 system clock cycles: 1 clock cycle to detect the interrup t and 5 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruction followed by a div as th e next instruction. in this case, the response time is 20 system clock cycles: 1 clock cycle to detect the in terrupt, 6 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 5 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt w ill not be servic ed until the current isr completes, including the reti and following instruction. note that the cpu is stalled during flash write operations and usb fifo movx accesses. interrupt ser- vice latency will be increased for in terrupts occurr ing while the cpu is stalled. the latency for these situa- tions will be determined by the standard interrupt service procedure (as described above) and the amount of time the cpu is stalled. 15.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
rev. 1.0 117 c8051f380/1/2/3/4/5/6/7 table 15.1. interrupt summary interrupt source interrupt vector priority order pending flag bit address? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) usb0 0x0043 8 special n n eusb0 (eie1.1) pusb0 (eip1.1) adc0 window com- pare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable coun- ter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie1.6) pcp1 (eip1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) nn et3 (eie1.7) pt3 (eip1.7) vbus level 0x007b 15 n/a n/a n/a evbus (eie2.0) pvbus (eip2.0) uart1 0x0083 16 ri1 (scon1.0) ti1 (scon1.1) nn es1 (eie2.1) ps1 (eip2.1) reserved 0x008b 17 n/a n/a n/a n/a n/a smb1 0x0093 18 si (smb1cn.0) y n esmb1 (eie2.3) psmb1 (eip2.3) timer 4 overflow 0x009b 19 tf4h (tmr4cn.7) tf4l (tmr4cn.6) yn et4 (eie2.4) pt4 (e!p2.4) timer 5 overflow 0x00a3 20 tf5h (tmr5cn.7) tf5l (tmr5cn.6) yn et5 (eie2.5) pt5 (e!p2.5)
c8051f380/1/2/3/4/5/6/7 118 rev. 1.0 sfr address = 0xa8; sfr page = all pages; bit-addressable sfr definition 15.1. ie: interrupt enable bit76543210 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it overrides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input.
rev. 1.0 119 c8051f380/1/2/3/4/5/6/7 sfr address = 0xb8; sfr page = all pages; bit-addressable sfr definition 15.2. ip: interrupt priority bit76543210 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level.
c8051f380/1/2/3/4/5/6/7 120 rev. 1.0 sfr address = 0xe6; sfr page = all pages sfr definition 15.3. eie1: ex tended interrupt enable 1 bit76543210 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 eusb0 esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. 5ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 1eusb0 enable usb (usb0) interrupt. this bit sets the masking of the usb0 interrupt. 0: disable all usb0 interrupts. 1: enable interrupt requests generated by usb0. 0 esmb0 enable smbus0 interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0.
rev. 1.0 121 c8051f380/1/2/3/4/5/6/7 sfr address = 0xf6; sfr page = all pages sfr definition 15.4. eip1: extended interrupt priority 1 bit76543210 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pusb0 psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts se t to low priority level. 1: timer 3 interrupts set to high priority level. 6pcp1 comparator1 (cp1) interru pt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete interrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. 1pusb0 usb (usb0) interrupt priority control. this bit sets the priority of the usb0 interrupt. 0: usb0 interrupt set to low priority level. 1: usb0 interrupt set to high priority level. 0 psmb0 smbus0 interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level.
c8051f380/1/2/3/4/5/6/7 122 rev. 1.0 sfr address = 0xe7; sfr page = all pages sfr definition 15.5. eie2: ex tended interrupt enable 2 bit76543210 name et5 et4 esmb1 es1 evbus type r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 unused read = 00b, write = don't care. 5et5 enable timer 5 interrupt. this bit sets the masking of the timer 5 interrupt. 0: disable timer 5 interrupts. 1: enable interrupt requests generated by the tf5l or tf5h flags. 4et4 enable timer 4 interrupt. this bit sets the masking of the timer 4 interrupt. 0: disable timer 4interrupts. 1: enable interrupt requests generated by the tf4l or tf4h flags. 3 esmb1 enable smbus1 interrupt. this bit sets the masking of the smb1 interrupt. 0: disable all smb1 interrupts. 1: enable interrupt requests generated by smb1. 2 reserved must write 0b. 1 es1 enable uart1 interrupt. this bit sets the masking of the uart1 interrupt. 0: disable uart1 interrupt. 1: enable uart1 interrupt. 0 evbus enable vbus level interrupt. this bit sets the masking of the vbus interrupt. 0: disable all vbus interrupts. 1: enable interrupt requests generated by vbus level sense.
rev. 1.0 123 c8051f380/1/2/3/4/5/6/7 sfr address = 0xf7; sfr page = all pages sfr definition 15.6. eip2: extended interrupt priority 2 bit76543210 name pt5 pt4 psmb1 ps1 pvbus type r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function :6 unused read = 00b, write = don't care. 5pt5 timer 5 interrupt priority control. this bit sets the priority of the timer 5 interrupt. 0: timer 5 interrupt set to low priority level. 1: timer 5 interrupt set to high priority level. 4pt4 timer 4 interrupt priority control. this bit sets the priority of the timer 4 interrupt. 0: timer 4 interrupt set to low priority level. 1: timer 4 interrupt set to high priority level. 3 psmb1 smbus1 interrupt priority control. this bit sets the priority of the smb1 interrupt. 0: smb1 interrupt set to low priority level. 1: smb1 interrupt set to high priority level. 2 reserved must write 0b. 1 ps1 uart1 interrupt priority control. this bit sets the priority of the uart1 interrupt. 0: uart1 interrupt set to low priority level. 1: uart1 interrupt set to high priority level. 0 pvbus vbus level interrupt priority control. this bit sets the priority of the vbus interrupt. 0: vbus interrupt set to low priority level. 1: vbus interrupt set to high priority level.
c8051f380/1/2/3/4/5/6/7 124 rev. 1.0 15.3. int0 and int1 external interrupt sources the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?25.1. timer 0 and timer 1? on page 263) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 15.7). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wi thout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplish ed by setting the associated bit in register pnskip (see section ?19.1. priority crossbar decoder? on page 151 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt re quest before execution of th e isr completes or anothe r interrupt re quest will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive
rev. 1.0 125 c8051f380/1/2/3/4/5/6/7 sfr address = 0xe4; sfr page = 0 sfr definition 15.7. it01cf: int0 /int1 configuration o bit76543210 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 00000001 bit name function 7in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin with out disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin with out disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7
c8051f380/1/2/3/4/5/6/7 126 rev. 1.0 16. reset sources reset circuitry allows the controller to be easily plac ed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lost, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divi ded by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 16.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf internal oscillator system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable xtal1 external oscillator drive errant flash operation rst (wired-or) power on reset 0 + - comparator 0 c0rsef vdd + - supply monitor enable low frequency oscillator xtal2
rev. 1.0 127 c8051f380/1/2/3/4/5/6/7 16.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 16.2. plots the power-on and v dd monitor event timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 0.3 ms. on exit from a power-on or v dd monitor reset, the porsf flag (rstsrc. 1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc register are indeterminate (porsf is cleared by all other resets). since all resets caus e program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was the cause of reset. the con- tent of internal data memory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 16.2. power-on and v dd monitor reset timing 16.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 16.2). when v dd returns to a level above v rst , the cip-51 will be released from the reset st ate. note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if v dd dropped below power-on reset vdd monitor reset rst t supply voltage logic high logic low t pordelay v d d v rst vdd
c8051f380/1/2/3/4/5/6/7 128 rev. 1.0 the level required for data retention. if the porsf flag reads 1, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined state (enabled/disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. i mportant note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in so me applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced between enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: 1. enable the v dd monitor (vdmen bit in vdm0cn = 1). 2. if necessary, wait for the v dd monitor to stabilize (see table 4.4 for the v dd monitor turn-on time). 3. select the v dd monitor as a reset source (porsf bit in rstsrc = 1). see figure 16.2 for v dd monitor timing; note that the power-on-reset delay is not incurred after a v dd monitor reset. see table 4.4 for complete electrical characteristics of the v dd monitor.
rev. 1.0 129 c8051f380/1/2/3/4/5/6/7 sfr address = 0xff; sfr page = all pages 16.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see table 4.4 for complete rst pin spec- ifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 16.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit th at is triggered by the system clock. if the system clock remains high or low for more than the mcd time-out, a reset will be generated. afte r a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the rese t source; otherwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the state of the rst pin is unaffected by this reset. 16.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, the c0rsef flag (rstsrc.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the rst pin is unaffected by this reset. sfr definition 16.1. vdm0cn: v dd monitor control bit7654321 0 name vdmen vddstat type r/wrrrrrr r reset varies varies varies varies varies varies varies varies bit name function 7vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys- tem resets until it is also selected as a reset source in register rstsrc (sfr def- inition 16.2). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. see table 4 .4 for the minimum v dd monitor turn-on time. 0: v dd monitor disabled. 1: v dd monitor enabled. 6vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5:0 unused read = 000000b; write = don?t care.
c8051f380/1/2/3/4/5/6/7 130 rev. 1.0 16.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as de scribed in section ?26.4. watchdog timer mode? on page 305; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is generated and the wdtrsf bit (rstsrc.5) is set to 1. the state of the rst pin is unaffected by this reset. 16.7. flash error reset if a flash program read, write, or erase operation targets an illegal ad dress, a system reset is generated. this may occur due to any of the following: ? programming hardware attempts to write or erase a flash location which is above the user code space address limit. ? a flash read from firmware is attempted above user code space. this occurs when a movc operation is attempted above the user code space address limit. ? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above the user code space address limit. ? a flash read, write, or erase attempt is restricted due to a flash security setting. ? a flash write or erase is attempted when the v dd monitor is not enabled. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 16.8. software reset software may force a reset by writ ing a 1 to the swrsf bit (rstsrc.4). the swrsf bit will read 1 fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset. 16.9. usb reset writing 1 to the usbrsf bit in register rstsrc selects usb0 as a reset source. with usb0 selected as a reset source, a system reset will be generat ed when either of the following occur: 1. reset signaling is detected on the usb network. the usb func tion controller (usb0) must be enabled for reset signaling to be detected. see section ?20. universa l serial bus controller (usb0)? on page 169 for information on the usb function controller. 2. a falling or rising voltage on the vbus pin. the usbrsf bit will read 1 following a usb reset. the state of the rst pin is unaffected by this reset.
rev. 1.0 131 c8051f380/1/2/3/4/5/6/7 sfr address = 0xef; sfr page = all pages sfr definition 16.2. r stsrc: reset source bit76543210 name usbrsf ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r/w r r/w r/w r r/w r/w r reset varies varies varies varies varies varies varies varies bit name description write read 7 usbrsf usb reset flag writing a 1 enables usb as a reset source. set to 1 if usb caused the last reset. 6ferror flash error reset flag. n/a set to 1 if flash read/write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a 1 enables comparator0 as a reset source (active-low). set to 1 if comparator0 caused the last reset. 4swrsf software reset force and flag. writing a 1 forces a sys- tem reset. set to 1 if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a 1 enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a 1 enables the v dd monitor as a reset source. writing 1 to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to 1 anytime a power- on or v dd monitor reset occurs. when set to 1 all other rstsrc flags are inde- terminate. 0pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. note: do not use read-modify-write operations on this register
c8051f380/1/2/3/4/5/6/7 132 rev. 1.0 17. flash memory on-chip, re-programmable flash memory is included for program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automat- ically timed by hardware for proper execution; data polling to dete rmine the end of th e write/erase opera- tion is not required. code execution is stalled during a flash write/erase operation. 17.1. programming the flash memory the simplest means of programming the flash memo ry is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial- ized device. for details on the c2 commands to progr am flash memory, see section ?27. c2 interface? on page 313. to ensure the integrity of flash contents, it is strongly recommended that the v dd monitor be left enabled in any system which writes or erases flash memory from code. it is also crucial to ensure that the flrt bit in register flscl be set to '1' if a clock speed higher than 25 mhz is being used for the device. 17.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, before flas h operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled unt il the next system reset. fl ash writes and erases will al so be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per- formed. the flkey register is det ailed in sfr definition 17.2. 17.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands. before writing to flash memory using movx, flash write operations must be enabled by: (1) writi ng the flash key codes in sequence to the flash lock register (flkey); and (2) setting the pswe program st ore write enable bit (psc tl.0) to logic 1 (this directs the movx writes to target flash memory). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed must be erased before a new value is written. the flash memory is organized in 512-byte pages. th e erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: 1. disable interrupts (recommended). 2. write the first key code to flkey: 0xa5. 3. write the second key code to flkey: 0xf1. 4. set the psee bit (register psctl). 5. set the pswe bit (register psctl). 6. using the movx instruction, write a data byte to an y location within the 512-byte page to be erased. 7. clear the pswe bit (register psctl). 8. clear the psee bit (register pscti).
rev. 1.0 133 c8051f380/1/2/3/4/5/6/7 17.1.3. flash write procedure bytes in flash memory can be written one byte at a time, or in groups of two. the flbwe bit in register pfe0cn (sfr definition ) controls w hether a single byte or a block of two bytes is written to flash during a write operation. when flbwe is cl eared to 0, the flash will be writte n one byte at a time. when flbwe is set to 1, the flash will be writ ten in two-byte blocks. block writes are performed in the same amount of time as single-byte writes, which can save time when storing large amounts of data to flash memory.dur- ing a single-byte write to fl ash, bytes are writte n individually, and a flash writ e will be performed after each movx write instruction. the recommended procedure for writing flash in single bytes is: 1. disable interrupts. 2. clear the flbwe bit (register pfe0cn) to select single-byte write mode. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. 8. clear the pswe bit. 9. re-enable interrupts. steps 5-7 must be repeated for each byte to be written. for block flash writes, the flash write procedure is only performed after the last byte of each block is writ- ten with the movx write instruction. a flash write block is two bytes long, from even addresses to odd addresses. writes must be performed sequentially (i.e . addresses ending in 0b and 1b must be written in order). the flash write will be perform ed following the movx writ e that targets the addr ess ending in 1b. if a byte in the block does not need to be updated in flash, it should be written to 0xff. the recommended procedure for writing flash in blocks is: 1. disable interrupts. 2. set the flbwe bit (register pfe0cn) to select block write mode. 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write the first data byte to the even block location (ending in 0b). 8. write the first key code to flkey: 0xa5. 9. write the second key code to flkey: 0xf1. 10.using the movx instruction, write the second data byte to the odd block location (ending in 1b). 11. clear the pswe bit. 12.re-enable interrupts. steps 5?10 must be repeated for each block to be written.
c8051f380/1/2/3/4/5/6/7 134 rev. 1.0 17.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. 17.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and th e program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before soft- ware can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 interface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01ff), where n is the 1s complement number represented by the security lock byte. note that the page containing the flash security lock byte is also lo cked when any other flash pages are locked. see exam- ple below. figure 17.1. flash program memory map and security byte the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, wr ites, and erases from the c2 debug in terface, user firmware executing on unlocked pages, and user firmware executing on locked pages. security lock byte: 11111101b 1s complement: 00000010b flash pages locked: 3 (2 + flash lock byte page) addresses locked: first two pages of flash: 0x0000 to 0x03ff flash lock byte page: (0xfa00 to 0xfbff for 64k devices; 0x7e00 to 0x7fff for 32k devices) access limit set according to the flash security lock byte c8051f380/2/4/6 0x0000 0xfbff lock byte reserved 0xfbfe 0xfc00 flash memory organized in 512-byte pages 0xfa00 unlocked flash pages locked when any other flash pages are locked c8051f381/3/5/7 0x0000 0x7fff lock byte 0x7ffe 0x7e00 unlocked flash pages
rev. 1.0 135 c8051f380/1/2/3/4/5/6/7 accessing flash from the c2 debug interface : 1. any unlocked page may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte may be r ead, written, or erased if it is unlocked. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing 1s to 0s in the lock byte) is not permitted. 6. unlocking flash pages (changing 0s to 1s in the lock byte) requires the c2 device erase command, which erases all flash pages including the page cont aining the lock byte and the lock byte itself. 7. the reserved area cannot be read, written, or erased. accessing flash from user firmware executing on an unlocked page : 1. any unlocked page except the page containing th e lock byte may be read, written, or erased. 2. locked pages cannot be read, written, or erased. 3. the page containing the lock byte cannot be erased. it may be read or written only if it is unlocked. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing 1s to 0s in the lock byte) is not permitted. 6. unlocking flash pages (changing 0s to 1s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will result in a flash error device reset. accessing flash from user firmware executing on a locked page : 1. any unlocked page except the page containing th e lock byte may be read, written, or erased. 2. any locked page except the page containing the lock byte may be read, written, or erased. 3. the page containing the lock byte cannot be erased. it may only be read or written. 4. reading the contents of the lock byte is always permitted. 5. locking additional pages (changing 1s to 0s in the lock byte) is not permitted. 6. unlocking flash pages (changing 0s to 1s in the lock byte) is not permitted. 7. the reserved area cannot be read, written, or erased. any attempt to access the reserved area, or any other locked page, will result in a flash error device reset.
c8051f380/1/2/3/4/5/6/7 136 rev. 1.0 sfr address =0x8f; sfr page = all pages sfr definition 17.1. psctl: program store r/w control bit76543210 name psee pswe type rrrrrrr/wr/w reset 00000000 bit name function 7:2 reserved must write 000000b. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; the movx write instruction targets flash memory.
rev. 1.0 137 c8051f380/1/2/3/4/5/6/7 sfr address = 0xb7; sfr page = all pages sfr definition 17.2. flk ey: flash lock and key bit76543210 name flkey[7:0] type r/w reset 00000000 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases ar e enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis- ter. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disabl ed, the flash will be perma- nently locked from writes or erasures until the next device reset. if an application never writes to flash, it can in tentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset.
c8051f380/1/2/3/4/5/6/7 138 rev. 1.0 sfr address = 0xb6; sfr page = all pages sfr definition 17.3. flscl: flash scale bit76543210 name fose reserved flrt reserved type r/w r/w r/w r/w reset 10000000 bit name function 7fose flash one-shot enable. this bit enables the flash read one-shot. when the flash one-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. at system clock frequencies below 10 mhz, disabling the flash one-shot will increase system power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. 6:5 reserved must write 00b. 4flrt flash read time. this bit should be programmed to the smallest allowed value, according to the system clock speed. 0: sysclk <= 25 mhz. 1: sysclk <= 48 mhz. 3:0 reserved must write 0000b.
rev. 1.0 139 c8051f380/1/2/3/4/5/6/7 18. oscillators and clock selection c8051f380/1/2/3/4/5/6/7 de vices include a programmab le internal high-frequenc y oscillator, a program- mable internal low-frequ ency oscillator, and an exte rnal oscillator drive circuit. the internal high-frequency oscillator can be enabled/disabled a nd calibrated using the oscicn and oscicl registers, as shown in figure 18.1. the internal low-fr equency oscillator can be enabled/disabled and calibrated using the osclcn register. the system clock can be sourced by the extern al oscillator circuit or either internal oscil- lator. both inte rnal oscillators offe r a selectable post- scaling featur e. the usb clock (usbclk) can be derived from the inte rnal oscillators or external oscillator. figure 18.1. oscillator options osc programmable internal 48 mhz clock input circuit en sysclk oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 oscxcn xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clksel usbclk2 usbclk1 usbclk0 clksl2 clksl1 clksl0 osclcn osclen osclrdy osclf3 osclf2 osclf1 osclf0 oscld1 oscld0 80 khz low frequency oscillator en 1, 2, 4, 8 oscld osclf osclf oscld usbclk clkmul mulen mulint mulrdy mulsel1 mulsel0 usbclk2-0 internal hfo / 8 exosc exosc / 2 exosc / 3 exosc / 4 internal lfo internal hfo osclen osclen xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 1, 2, 4, 8 2 2 (12 mhz) (24 mhz) (48 mhz)
c8051f380/1/2/3/4/5/6/7 140 rev. 1.0 18.1. system clock selection the clksl[2:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[2:0] must be set to 001b for t he system clock to run from the exte rnal oscillator; however the exter- nal oscillator may still clock certain per ipherals (timers, pca) when the inte rnal oscillator is selected as the system clock. the system clock may be switched on-the-fly between the intern al oscillators and external oscillator so long as the selected clock source is en abled and running. the internal high-frequency and low-frequency osc illators require little start-up time and may be selected as the system clock immediately fo llowing the register writ e which enables the osc illator. the external rc and c modes also typically require no startup time. 18.2. usb clock selection the usbclk[2:0] bits in register cl ksel select which oscillator source is used as the usb clock. the usb clock may be derived from the internal oscillators, a divided vers ion of the intern al high-frequency oscillator, or a divided version of the external os cillator. note that the u sb clock must be 48 mhz when operating usb0 as a full speed function; the usb cl ock must be 6 mhz when operating usb0 as a low speed function. see sfr definition 18.1 for usb clock selection options. some example usb clock configurations for full and low speed mode are given below: usb full speed (48 mhz) internal oscillator clock signal input source selection register bit settings usb clock internal osc illator* usbclk = 000b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock external oscillator usbclk = 010b external oscillator c mos oscillator mode 48 mhz oscillator xoscmd = 010b note: clock recovery must be enabled for this configuration. usb low speed (6 mhz) internal oscillator clock signal input source selection register bit settings usb clock internal osc illator / 8 usbclk = 001b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock external oscillator / 4 usbclk = 101b external oscillator c mos oscillator mode 24 mhz oscillator xoscmd = 010b crystal oscillator mode 24 mhz oscillator xoscmd = 110b xfcn = 111b
rev. 1.0 141 c8051f380/1/2/3/4/5/6/7 sfr address = 0xa9; sfr page = all pages sfr definition 18.1. clksel: clock select bit76543210 name usbclk[2:0] outclk clksl[2:0] type r r/w r/w r/w reset 00000000 bit name function 7 unused read = 0b; write = don?t care 6:4 usbclk[2:0] usb clock source select bits. 000: usbclk derived from the in ternal high-fre quency oscillator. 001: usbclk derived from the internal high-f requency oscillator / 8. 010: usbclk derived from the external oscillator. 011: usbclk derived from the external oscillator/2. 100: usbclk derived from the external oscillator/3. 101: usbclk derived from the external oscillator/4. 110: usbclk derived from the in ternal low-frequ ency oscillator. 111: reserved. 3 outclk crossbar clock out select. if the sysclk signal is enabled on the crossbar, this bit selects between outputting sysclk and sysclk synchronized with the port i/o pins. 0: enabling the crossbar sysclk signal outputs sysclk. 1: enabling the crossbar sysclk signal outputs sysclk synchronized with the port i/o. 2:0 clksl[2:0] system clock source select bits. 000: sysclk derived from th e internal high-fr equency oscillator and scaled per the ifcn bits in register oscicn. 001: sysclk derived from the external oscillator circuit. 010: sysclk derived from the internal high-frequency oscillator / 2. 011: sysclk derived from the inte rnal high-frequency oscillator. 100: sysclk derived from th e internal low- frequency oscillato r and scaled per the oscld bits in register osclcn. 101-111: reserved.
c8051f380/1/2/3/4/5/6/7 142 rev. 1.0 18.3. programmable internal high-frequency (h-f) oscillator all c8051f380/1/2/3/4/5/ 6/7 devices include a pr ogrammable internal high -frequency os cillator that defaults as the system clock after a system reset. th e internal oscillator period can be adjusted via the oscicl register as defined by sfr definition 18.2. on c8051f380/1/2/3/4/5/6/7 devices, oscicl is factory calibrated to obtain a 48 mhz base frequency. note that the system clock may be derived from the prog rammed internal oscillator di vided by 1, 2, 4, or 8 after a divide by 4 stage, as defined by the ifcn bits in register oscicn. the divide value defaults to 8 fol- lowing a reset, which results in a 1.5 mhz system clock. 18.3.1. internal os cillator suspend mode when software writes a logic 1 to suspend (oscicn.5) , the internal oscillator is suspended. if the sys- tem clock is derived from t he internal oscillator, the input clock to the peripheral or cip-51 will be stopped until a non-idle usb event is detected or a rising or falling edge occurs on the vbus signal. note that the usb transceiver can still detect usb events when it is disabled. when one of the oscillator awakening events occur, the internal oscillator, cip-51 , and affected peripherals resume normal operation. the cpu resumes executi on at the instruction following the write to the sus- pend bit. note: the prefetch engine can be turned off in suspend mode to save power. additionally, both voltage regulators (reg0 and reg1) have low-power modes for additional power savings in suspend mode. sfr address = 0xb3; sfr page = all pages sfr definition 18.2. oscicl: intern al h-f oscillator calibration bit76543210 name oscicl[6:0] type rr/w reset 0 varies varies varies var ies varies varies varies bit name function 7 unused read = 0; write = don?t care 6:0 oscicl[6:0] internal oscillator calibration bits. these bits determine the internal oscillato r period. when set to 0000000b, the h-f oscillator operates at its fa stest setting. when set to 111 1111b, the h-f oscillator operates at its slowest setting. the reset value is factory calibrated to generate an internal oscillator frequency of 48 mhz. oscicl should only be changed by firm- ware when the h-f oscillator is disabled (ioscen = 0).
rev. 1.0 143 c8051f380/1/2/3/4/5/6/7 sfr address = 0xb2; sfr page = all pages sfr definition 18.3. oscicn: inte rnal h-f oscillator control bit76 5 43210 name ioscen ifrdy suspend ifcn[1:0] type r/w r r/w r r r r/w reset 11000000 bit name function 7ioscen internal h-f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is no t running at pr ogrammed frequency. 1: internal h-f oscillator is running at progr ammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter- nal oscillator resumes ope ration when one of th e suspend mode awakening events occurs. 4:2 unused read = 000b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator fre quency divider control bits. the internal h-f oscillator is divided by the ifcn bit setting after a divide-by-4 stage. 00: sysclk can be derived from internal h-f oscillator divided by 8 (1.5 mhz). 01: sysclk can be derived from internal h-f oscillator divided by 4 (3 mhz). 10: sysclk can be derived from internal h-f oscillator divided by 2 (6 mhz). 11: sysclk can be derived from internal h-f oscillator divid ed by 1 (12 mhz).
c8051f380/1/2/3/4/5/6/7 144 rev. 1.0 18.4. clock multiplier the c8051f380/1/2/3/4/5/6/7 device includes a 48 mhz high-fre quency oscillator instead of a 12 mhz oscillator and a 4x clock mu ltiplier, so the usb0 module can be r un directly from the internal high-fre- quency oscillator. for compatibilit y with c8051f34x and c8051f32x dev ices however, the clkmul regis- ter (sfr definition 18.4) behaves as if the clock multiplier is present and working. sfr address = 0xb9; sfr page = 0 sfr definition 18.4. clkmul: clock multiplier control bit76543210 name mulen mulinit mulrdy mulsel[1:0] type rrrrrr r reset 11100000 bit name description 7mulen clock multiplier enable bit. this bit always reads 1. 6mulinit clock multiplier initialize bit. this bit always reads 1. 5 mulrdy clock multiplier ready bit. this bit always reads 1. 4:2 unused read = 000b; write = don?t care 1:0 mulsel[1:0] clock multiplier input select bits. these bits always read 00.
rev. 1.0 145 c8051f380/1/2/3/4/5/6/7 18.5. programmable internal low-frequency (l-f) oscillator all c8051f380/1/2/3/4/5/6/7 devices include a progra mmable low-frequency inter nal oscillator, which is calibrated to a nominal frequency of 80 khz. the low-frequency oscillator circuit includ es a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the oscld bits in the osclcn register (see sfr definition 18.5). additionally, the osclf[3:0] bits ca n be used to adjust the oscillator?s output frequency. 18.5.1. calibrating the internal l-f oscillator timers 2 and 3 inclu de capture functions that can be used to capture the oscillator frequency, when run- ning from a known time base. when either timer 2 or timer 3 is configured fo r l-f oscillator capture mode, a falling edge (t imer 2) or rising edge (tim er 3) of the low-frequency o scillator?s output will cause a capture event on the corresponding timer. as a capture event occurs, the current timer value (tmrnh:tmrnl) is copied into the timer reload regi sters (tmrnrlh:tmrnrll). by recording the differ- ence between two successive time r capture values, the lo w-frequency oscillator?s period can be calcu- lated. the osclf bits can then be adjusted to produce t he desired oscilla tor frequency. sfr address = 0x86; sfr page = all pages sfr definition 18.5. osclcn: inte rnal l-f oscill ator control bit76543210 name osclen osclrdy osclf[3:0] oscld[1:0] type r/w r r.w r/w reset 0 0 varies varies varies varies 0 0 bit name function 7osclen internal l-f oscillator enable. 0: internal l-f os cillator disabled. 1: internal l-f oscillator enabled. 6osclrdy internal l-f oscillator ready. 0: internal l-f oscillator frequency not stabilized. 1: internal l-f oscilla tor frequency stabilized. note: osclrdy is only set back to 0 in the event of a device reset or a change to the oscld[1:0] bits. 5:2 osclf[3:0] internal l-f oscillator frequency control bits. fine-tune control bits for the internal l-f oscillator fr equency. when set to 0000b, the l-f oscillator oper ates at its fastest setting. when set to 1111b, th e l-f oscillator operates at its slowest setting. the osclf bits should only be changed by firmware when the l-f oscillator is disabled (osclen = 0). 1:0 oscld[1:0] internal l-f oscillator divider select. 00: divide by 8 selected. 01: divide by 4 selected. 10: divide by 2 selected. 11: divide by 1 selected.
c8051f380/1/2/3/4/5/6/7 146 rev. 1.0 18.6. external osci llator drive circuit the external oscillator circuit may driv e an external crystal, ce ramic resonator, capacito r, or rc network. a cmos clock may also provide a clock input. figure 18.1 shows a block diagram of the four external oscil- lator options. the external oscillator is enabled a nd configured using the oscxcn register (see sfr defi- nition 18.6). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal /resonator mo de, port pins p0.2 and p0.3 are used as xtal1 and xtal2, respectively. when th e external oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pin used by the oscillator circui t; see section ?19.1. priority crossbar decoder? on page 151 for crossbar co nfiguration. additionally, when usin g the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?19.2. port i/o initialization? on page 155 for deta ils on port inpu t mode selection. the external osc illator output may be select ed as the system clock or used to clock some of the digital peripherals (e.g. timers, pca, etc.). see the data sheet chapters for each digital peripheral for details. see section ?4. electrical characteristics? on p age 34 for complete osc illator specifications. 18.6.1. external crystal mode if a crystal or ceramic resonator is used as the ex ternal oscillator, the cr ystal/resonator and a 10 m ?? resis- tor must be wired across the xtal1 and xtal2 pins as shown in figure 18.1, ?crystal mode?. appropriate loading capacitors should be added to xtal1 and xta l2, and both pins should be configured for analog i/o with the digital output drivers disabled. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are ?in series? as seen by the crystal and ?in parallel? with the stray capacitance of the xtal1 and xtal2 pins. note: the recommended load capacitance depends upon the crystal and the manufacturer. refer to the crystal data sheet when completing these calculations. the equation for determining the load capacitance for two capacitors is where: c a and c b are the capacitors connec ted to the crystal leads. c s is the total stray capacitance of the pcb. the stray capacitance for a typical layout where the crysta l is as close as possible to the pins is 2-5 pf per pin. if c a and c b are the same (c), then the equation becomes for example, a tuning-fork crystal of 32 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 18.1, option 1. with a stray capacitance of 3 pf per pin (6 pf total), the 13 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 18.2. c l c a c b ? c a c b + -------------------- c s + = c l c 2 --- - c s + =
rev. 1.0 147 c8051f380/1/2/3/4/5/6/7 figure 18.2. external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to th e xtal pins on the device. the traces should be as short as possible and shielded with ground plane from any other traces whic h could introduce noise or interference. when using an external crystal, the external oscillator drive circuit must be configured by software for crystal oscillator mode or crystal oscillator mode with divide by 2 stage . the divide by 2 stage ensures that the clock derived from the ex ternal oscillator has a duty cycle of 50%. th e external oscillator fre- quency control value (xfcn) must also be specifie d based on the crystal frequency (see sfr definition 18.6). when the crystal oscillator is first enabled, the external osc illator valid detector allo ws software to deter- mine when the external system clock is valid and running. sw itching to the external oscilla tor before the crystal oscillator has stabilized can re sult in unpredictable behavior. th e recommended procedure for start- ing the crystal is: 1. configure xtal1 and xtal2 for analog i/o. 2. disable the xtal1 and xtal2 digital output drivers by writing 1s to the appropriate bits in the port latch register. 3. configure and enable th e external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld > 1. 6. switch the system clock to the external oscillator. 13 pf 13 pf 32 khz xtal1 xtal2 10 m ?
c8051f380/1/2/3/4/5/6/7 148 rev. 1.0 18.6.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 18.1, ?rc mode?. the capacitor should be no greater than 100 pf; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network valu e to produce the desired frequency of o scillation, according to equation , where f = the frequency of os cillation in mhz, c = the capacitor value in pf, and r = the pull- up resistor value in k ? . equation 18.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sf r definition 18.6, the required xfcn setting is 010b. 18.6.3. external capacitor example if a capacitor is used as an external oscillator for the mcu, the circui t should be configured as shown in figure 18.1, ?c mode?. the capacitor should be no greater than 100 pf; however, for very small capaci- tors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find the frequen cy of oscillation according to equati on , where f = the fr equency of oscil- lation in mhz, c = the capacitor value in pf, and v dd = the mcu power supply in volts. equation 18.2. c mode oscillator frequency for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, sele ct the k factor from the table in sfr definition 18.6 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf. f 1.23 10 3 ? rc ? ?? ? = fkf ?? cv dd ? ?? ? =
rev. 1.0 149 c8051f380/1/2/3/4/5/6/7 sfr address = 0xb1; sfr page = all pages sfr definition 18.6. oscxcn: ex ternal oscillator control bit76543210 name xclkvld xoscmd[2:0] xfcn[2:0] type rr/wrr/w reset 00000000 bit name function 7 xclkvld external oscillator valid flag. provides external oscillator status and is valid at all times for all modes of opera- tion except external cmos clock mode and external cmos clock mode with divide by 2. in these modes, xclkvld always returns 0. 0: external oscillator is unused or not yet stable. 1: external oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide-by-2 stage. 100: rc oscillator mode wi th divide-by-2 stage. 101: capacitor oscillator mo de with divide-by-2 stage. 110: crystal oscillator mode. 111: crystal oscillator mode with divide-by-2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ?? 20 khz f ?? 25 khz k factor = 0.87 001 20 khz ?? f ?? 58 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 58 khz ?? f ?? 155 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 155 khz ?? f ?? 415 khz 100 khz ?? f ?? 200 khz k factor = 22 100 415 khz ?? f ?? 1.1 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.1 mhz ?? f ?? 3.1 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 3.1 mhz ?? f ?? 8.2 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 8.2 mhz ?? f ?? 25 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590
c8051f380/1/2/3/4/5/6/7 150 rev. 1.0 19. port input/output digital and analog resources are available through 40 i/o pins (c8051f380/2/4/6) or 25 i/o pins (c8051f381/3/5/7). port pins are organized as shown in figure 19.1. each of the port pins can be defined as general-purpose i/o (gpio) or analog input; port pi ns p0.0-p3.7 can be assigned to one of the internal digital resources as shown in figure 19.3. the desig ner has complete control over which functions are assigned, limited only by th e number of physical i/o pins. this re source assign ment flexibility is achieved through the use of a priority crossbar decoder. note t hat the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital reso urces to the i/o pins based on the priority decoder (figure 19.3 and figure 19.4). the registers xbr0, xbr 1, and xbr2 defined in sfr definition 19.1, sfr definition 19.2, and sfr definition 19.3, are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 19.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port ou tput mode registers (pnmdout, where n = 0,1,2,3,4). figure 19.1. port i/o functional block diagram (port 0 through port 3) xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart0 (internal digital signals) highest priority lowest priority sysclk 2 smbus0 t0, t1 2 6 pca cp1 outputs 2 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 p2 i/o cells p2.0 p2.7 8 p3 i/o cells p3.0 8 (port latches) p0 8 8 8 8 p1 p2 p3 *p3.1-p3.7 only available on 48-pin packages uart1 2 p3.7* (p0.0-p0.7) (p1.0-p1.7) (p2.0-p2.7) (p3.0-p3.7*) 2 smbus1
rev. 1.0 151 c8051f380/1/2/3/4/5/6/7 figure 19.2. port i/o cell block diagram 19.1. priority crossbar decoder the priority crossbar decoder (figure 19.3) assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the leas t-significant unassigned port pin is assigned to that resource (excluding uart0, which is always at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additi onally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pn skip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to the vref signal , external oscillator pins (xtal1, xtal2), the adc?s external conver- sion start signal (cnvstr), emif control signals, and any selected adc or comparator inputs. the pnskip registers may also be used to skip pins to be used as gpio. the crossbar skips selected pins as if they were already assigned, and moves to the nex t unassigned pin. figure 19.3 shows all the possible pins available to each peripheral. figure 19.4 shows an example crossbar configuration with no port pins skipped. figure 19.5 shows the same crossbar example with pins p0.2, p0.3, and p1.0 skipped. registers xbr0, xbr1, and xbr2 are used to assign the digital i/o resources to the physical i/o port pins. note that when either smbus is selected, the crossbar assigns both pins associated with the smbus (sda and scl); when either uart is selected, the cr ossbar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bo otloading purposes: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standa rd port i/os appear contiguously after the priori- tized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1-nssmd0 bits in register spi 0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. gnd port-outenable port-output push-pull vdd vdd weak-pullup (weak) port pad analog input analog select port-input
c8051f380/1/2/3/4/5/6/7 152 rev. 1.0 figure 19.3. peripheral availability on port i/o pins tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 pin number 48-pin special function signals xtal1 0 0 0 0 0 0 0 0 p0skip pin skip settings xtal2 cp1 cp1a sck miso mosi nss* cex3 cex4 0 1 2 3 4 5 6 7 ale rd 0 0 0 0 0 0 0 0 p1skip cnvstr vref wr 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 p2skip 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 p3skip the crossbar peripherals are assigned in priority order from top to bottom, according to this diagram. these boxes represent port pins which can potentially be assigned to a peripheral. special function signals are not assigned by the cr ossbar. when these signals are enabled, the crossbar should be manually configured to skip the corresponding port pins. pins can be ?skipped? by setting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. tx1 rx1 sda1 scl1 32-pin special function signals xtal2 cnvstr xtal1 vref unavailable on 32-pin packages
rev. 1.0 153 c8051f380/1/2/3/4/5/6/7 figure 19.4. crossbar priority decoder in example configuration (no pins skipped) tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number 48-pin special function signals xtal1 0 0 0 0 0 0 0 0 p0skip pin skip settings xtal2 cp1 cp1a sck miso mosi nss* cex3 cex4 0 1 2 3 4 5 6 7 p1 ale rd 0 0 0 0 0 0 0 0 p1skip cnvstr vref wr 0 1 2 3 4 5 6 7 p2 0 0 0 0 0 0 0 0 p2skip 0 1 2 3 4 5 6 7 p3 0 0 0 0 0 0 0 0 p3skip this example shows a crossbar configuration with xbr0 = 0x07 and xbr1 = 0x43. these boxes represent port pins which are assigned to a peripheral. tx1 rx1 sda1 scl1 32-pin special function signals xtal2 cnvstr xtal1 vref unavailable on 32-pin packages tx0 and rx0 are fixed at these locations the other peripherals are assigned based on pin availability, in priority order.
c8051f380/1/2/3/4/5/6/7 154 rev. 1.0 figure 19.5. crossbar priority decoder in example configuration (3 pins skipped) tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number 48-pin special function signals xtal1 0 0 1 1 0 0 0 0 p0skip pin skip settings xtal2 cp1 cp1a sck miso mosi nss* cex3 cex4 0 1 2 3 4 5 6 7 p1 ale rd 1 0 0 0 0 0 0 0 p1skip cnvstr vref wr 0 1 2 3 4 5 6 7 p2 0 0 0 0 0 0 0 0 p2skip 0 1 2 3 4 5 6 7 p3 0 0 0 0 0 0 0 0 p3skip this example shows a crossbar configuration with xbr0 = 0x07 and xbr1 = 0x43. these boxes represent port pins which are assigned to a peripheral. tx1 rx1 sda1 scl1 32-pin special function signals xtal2 cnvstr xtal1 vref unavailable on 32-pin packages p0.2 skipped p0.3 skipped p1.0 skipped if a pin is skipped, it is not available for assignment, and the crossbar will move the assignment to the next available pin
rev. 1.0 155 c8051f380/1/2/3/4/5/6/7 19.2. port i/o initialization port i/o initialization consis ts of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals (xbr0, xbr1). 5. enable the crossbar (xbare = 1). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog inpu t. pins configured as digita l inputs may still be used by an alog peripherals ; however this practice is not recommended. to configure a port pin for digital input, write 0 to the corresponding bit in register pnmdout, and write 1 to the corresponding port latch (register pn). additionally, all analog input pins should be configured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. the output driver characteristics of the i/o pins are defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this are the smbus (s da, scl, sda1 and scl1) pins, wh ich are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is 0, a weak pull-up is enabled for all port i/o configured as open-drain. weakpud does not affect the push-pull port i/o. furthermore, the weak pull-up is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the appr opriate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out using the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. important note: the crossbar must be enabled to use ports p0, p1, p2, and p3 as standard port i/o in output mode. these port output drivers are disabled while the crossbar is disabled. port 4 always func- tions as standard gpio.
c8051f380/1/2/3/4/5/6/7 156 rev. 1.0 sfr address = 0xe1; sfr page = all pages sfr definition 19.1. xbr0: port i/o crossbar register 0 bit76543210 name cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1a unavailable at port pin. 1: asynchronous cp1a routed to port pin. 6cp1e comparator1 output enable. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. 5cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0a unavailable at port pin. 1: asynchronous cp0a routed to port pin. 4cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 2smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 1spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5.
rev. 1.0 157 c8051f380/1/2/3/4/5/6/7 sfr address = 0xe2; sfr page = all pages sfr definition 19.2. xbr1: port i/o crossbar register 1 bit7 6543210 name weakpud xbare t1e t0e ecie pca0me[2:0] type r/w r/wr/wr/wr/wr/wr/wr/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2:0 pca0me[2:0] pca module i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3 routed to port pins. 11x: reserved.
c8051f380/1/2/3/4/5/6/7 158 rev. 1.0 sfr address = 0xe3; sfr page = all pages 19.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports 3-0 are accessed through corresponding special function registers (sfrs) that are both byte addressable and bit addressable. port 4 (c8051f380/2/4/6 only) uses an sfr which is byte-addressable. when writing to a port, the value wr itten to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/o pin). the except ion to this is the executio n of the read-modify-write instructions. the read-mod ify-write instructions when operating on a port sfr are the following: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an individual bit in a port sfr. for these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr. sfr definition 19.3. xbr2: port i/o crossbar register 2 bit7 6543210 name smb1e urt1e type r/w r/wr/wr/wr/wr/wr/wr/w reset 0 0000000 bit name function 7:2 reserved must write 000000b 1smb1e smbus1 i/o enable. 0: smbus1 i/o unavailable at port pins. 1: smbus1 i/o rout ed to port pins. 0urt1e uart1 i/oenable. 0: uart1 i/o unavailable at port pins. 1: uart1 tx1, rx1 routed to port pins.
rev. 1.0 159 c8051f380/1/2/3/4/5/6/7 sfr address = 0x80; sfr page = all pages; bit addressable sfr address = 0xf1; sfr page = all pages sfr definition 19.4. p0: port 0 bit76543210 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. sfr definition 19.5. p0mdi n: port 0 input mode bit76543210 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode.
c8051f380/1/2/3/4/5/6/7 160 rev. 1.0 sfr address = 0xa4; sfr page = all pages sfr address = 0xd4; sfr page = all pages sfr definition 19.6. p0mdo ut: port 0 output mode bit76543210 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the correspondi ng bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. sfr definition 19.7. p0skip: port 0 skip bit76543210 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar.
rev. 1.0 161 c8051f380/1/2/3/4/5/6/7 sfr address = 0x90; sfr page = all pages; bit addressable sfr address = 0xf2; sfr page = all pages sfr definition 19.8. p1: port 1 bit76543210 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. sfr definition 19.9. p1mdi n: port 1 input mode bit76543210 name p1mdin[7:0] type r/w reset 1*1111111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode.
c8051f380/1/2/3/4/5/6/7 162 rev. 1.0 sfr address = 0xa5; sfr page = all pages sfr address = 0xd5; sfr page = all pages sfr definition 19.10. p1mdout: port 1 output mode bit76543210 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the correspondi ng bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. sfr definition 19.11. p1skip: port 1 skip bit76543210 name p1skip[7:0] type r/w reset 00000000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar.
rev. 1.0 163 c8051f380/1/2/3/4/5/6/7 sfr address = 0xa0; sfr page = all pages; bit addressable sfr address = 0xf3; sfr page = all pages sfr definition 19.12. p2: port 2 bit76543210 name p2[7:0] type r/w reset 11111111 bit name description write read 7:0 p2[7:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. sfr definition 19.13. p2mdin: port 2 input mode bit76543210 name p2mdin[7:0] type r/w reset 11111111 bit name function 7:0 p2mdin[7:0] analog configuration bits for p2.7?p2.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode.
c8051f380/1/2/3/4/5/6/7 164 rev. 1.0 sfr address = 0xa6; sfr page = all pages sfr address = 0xd6; sfr page = all pages sfr definition 19.14. p2mdout: port 2 output mode bit76543210 name p2mdout[7:0] type r/w reset 00000000 bit name function 7:0 p2mdout[7:0] output configuration bits for p2.7?p2.0 (respectively). these bits are ignored if the correspondi ng bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. sfr definition 19.15. p2skip: port 2 skip bit76543210 name p2skip[7:0] type r/w reset 00000000 bit name function 7:0 p2skip[3:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar.
rev. 1.0 165 c8051f380/1/2/3/4/5/6/7 sfr address = 0xb0; sfr page = all pages; bit addressable sfr address = 0xf4; sfr page = all pages sfr definition 19.16. p3: port 3 bit76543210 name p3[7:0] type r/w reset 11111111 bit name description write read 7:0 p3[7:0] port 3 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p3.n port pin is logic low. 1: p3.n port pin is logic high. sfr definition 19.17. p3mdin: port 3 input mode bit76543210 name p3mdin[7:0] type r/w reset 11111111 bit name function 7:0 p3mdin[7:0] analog configuration bits for p3.7?p3.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p3.n pin is configured for analog mode. 1: corresponding p3.n pin is not configured for analog mode.
c8051f380/1/2/3/4/5/6/7 166 rev. 1.0 sfr address = 0xa7; sfr page = all pages sfr address = 0xdf; sfr page = all pages sfr definition 19.18. p3mdout: port 3 output mode bit76543210 name p3mdout[7:0] type r/w reset 00000000 bit name function 7:0 p3mdout[7:0] output configuration bits for p3.7?p3.0 (respectively). these bits are ignored if the correspondi ng bit in register p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. sfr definition 19.19. p3skip: port 3 skip bit76543210 name p3skip[7:0] type r/w reset 00000000 bit name function 7:0 p3skip[3:0] port 3 crossbar skip enable bits. these bits select port 3 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p3.n pin is not skipped by the crossbar. 1: corresponding p3.n pin is skipped by the crossbar.
rev. 1.0 167 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc7; sfr page = all pages sfr address = 0xf5; sfr page = all pages sfr definition 19.20. p4: port 4 bit76543210 name p4[7:0] type r/w reset 11111111 bit name description write read 7:0 p4[7:0] port 4 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p4.n port pin is logic low. 1: p4.n port pin is logic high. sfr definition 19.21. p4mdin: port 4 input mode bit76543210 name p4mdin[7:0] type r/w reset 11111111 bit name function 7:0 p4mdin[7:0] analog configuration bits for p4.7?p4.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p4.n pin is configured for analog mode. 1: corresponding p4.n pin is not configured for analog mode.
c8051f380/1/2/3/4/5/6/7 168 rev. 1.0 sfr address = 0xae; sfr page = all pages sfr definition 19.22. p4mdout: port 4 output mode bit76543210 name p4mdout[7:0] type r/w reset 00000000 bit name function 7:0 p4mdout[7:0] output configuration bits for p4.7?p4.0 (respectively). these bits are ignored if the correspondi ng bit in register p4mdin is logic 0. 0: corresponding p4.n output is open-drain. 1: corresponding p4.n output is push-pull.
rev. 1.0 169 c8051f380/1/2/3/4/5/6/7 20. universal serial bus controller (usb0) c8051f380/1/2/3/4/5/6/7 devices include a complete full/low speed usb function for usb peripheral implementations. the usb function controller (usb0) consists of a serial interface engine (sie), usb transceiver (including matching resistors and configurable pull-up resistors), 1 kb fifo block, and clock recovery mechanism for crystal-less operation. no external components are required. the usb function controller and transceiver is universal serial bus sp ecification 2.0 compliant. figure 20.1. usb0 block diagram important note: this document assumes a comprehe nsive understanding of the usb protocol. terms and abbreviations used in this document are defined in th e usb specification. we encourage you to review the latest version of the usb specification before proceeding. note: the c8051f380/1/2/3/4/5/6/7 cannot be used as a usb host device. 20.1. endpoint addressing a total of eight endpoint pipes are available. the c ontrol endpoint (endpoint0) always functions as a bi- directional in/out endpoint. the other endpoints are implemented as three pairs of in/out endpoint pipes: transceiver serial interface engine (sie) usb fifos (1k ram) d+ d- vdd endpoint0 in/out endpoint1 in out endpoint2 in out endpoint3 in out data transfer control cip-51 core usb control, status, and interrupt registers
c8051f380/1/2/3/4/5/6/7 170 rev. 1.0 20.2. usb transceiver the usb transceiver is configured via the usb0xcn regi ster shown in sfr definition 20.1. this configu- ration includes transceiver enable/disable, pull-up resistor enable/disable, and device speed selection (full or low speed). when bit speed = 1, usb0 oper ates as a full speed usb function, and the on-chip pull-up resistor (if enabled) appears on the d+ pin. when bit speed = 0, usb0 operates as a low speed usb function, and the on-chip pull-up resistor (if ena bled) appears on the d- pin. bits4-0 of register usb0xcn can be used for transceiver testing as described in sfr definition 20.1. the pull-up resistor is enabled only when vbus is present (see section ?8 .1.2. vbus detection? on pa ge 69 for details on vbus detection). important note: the usb clock should be active before the transceiver is enabled. table 20.1. endpoint addressing scheme endpoint associated pipes usb protocol address endpoint0 endpoint0 in 0x00 endpoint0 out 0x00 endpoint1 endpoint1 in 0x81 endpoint1 out 0x01 endpoint2 endpoint2 in 0x82 endpoint2 out 0x02 endpoint3 endpoint3 in 0x83 endpoint3 out 0x03
rev. 1.0 171 c8051f380/1/2/3/4/5/6/7 sfr address = 0xd7; sfr page = all pages sfr definition 20.1. usb0xcn : usb0 transceiver control bit76543210 name pren phyen speed phytst[1:0] dfrec dp dn type r/w r/w r/w r/w r r r reset 00000000 bit name function 7pren internal pull-up resistor enable. the location of the pull-up resistor (d+ or d-) is de termined by the speed bit. 0: internal pull-up resistor disabled (device effectively detached from usb network). 1: internal pull-up resistor enabled when vbus is present (device attached to the usb network). 6 phyen physical layer enable. 0: usb0 physical layer transceiver disabled (suspend). 1: usb0 physical layer tran sceiver enabled (normal). 5 speed usb0 speed select. this bit selects the usb0 speed. 0: usb0 operates as a low speed device. if enabled, the internal pull-up resistor appears on the d? line. 1: usb0 operates as a full speed device. if enabled, the internal pull-up resistor appears on the d+ line. 4:3 phytst[1:0] physical layer test bits. 00: mode 0: normal (non-test mode) (d+ = x, d- = x) 01: mode 1: differential 1 forced (d+ = 1, d- = 0) 10: mode 2: differential 0 forced (d+ = 0, d- = 1) 11: mode 3: single-ended 0 forced (d+ = 0, d? = 0) 2dfrec differential receiver bit the state of this bit indicates the current differential value present on the d+ and d- lines when phyen = 1. 0: differential 0 signalling on the bus. 1: differential 1 signalling on the bus. 1dp d+ signal status. this bit indicates the curren t logic level of the d+ pin. 0: d+ signal currently at logic 0. 1: d+ signal currently at logic 1. 0dn d- signal status. this bit indicates the curren t logic level of the d- pin. 0: d- signal currently at logic 0. 1: d- signal currently at logic 1.
c8051f380/1/2/3/4/5/6/7 172 rev. 1.0 20.3. usb register access the usb0 controller registers listed in table 20. 2 are accessed through two sfrs: usb0 address (usb0adr) and usb0 data (usb0dat). the usb0adr register se lects which usb register is targeted by reads/writes of the usb0 dat register. see figure 20.2. endpoint control/status registers ar e accessed by first writing the usb re gister index with the target end- point number. once the target endpoint number is writ ten to the index register, the control/status registers associated with the target endpoint may be access ed. see the ?indexed registers? section of table 20.2 for a list of endpoint control/status registers. important note : the usb clock must be active when accessing usb registers. figure 20.2. usb0 register access scheme usb controller fifo access index register endpoint0 control/ status registers endpoint1 control/ status registers endpoint2 control/ status registers endpoint3 control/ status registers common registers interrupt registers 8051 sfrs usb0adr usb0dat
rev. 1.0 173 c8051f380/1/2/3/4/5/6/7 sfr address = 0x96; sfr page = all pages sfr definition 20.2. usb0adr : usb0 indirect address bit76543210 name busy autord usbaddr[5:0] type r/w r/w r/w reset 00000000 bit name description write read 7busy usb0 register read busy flag. this bit is used during indirect usb0 register accesses. 0: no effect. 1: a usb0 indirect regis- ter read is initiated at the address specified by the usbaddr bits. 0: usb0dat register data is valid. 1: usb0 is busy access- ing an indirect register; usb0dat register data is invalid. 6autord usb0 register auto-read flag. this bit is used for block fifo reads. 0: busy must be written manually for each usb0 indirect register read. 1: the next indirect register read will automatica lly be initiated when software reads usb0dat (usbaddr bits will not be changed). 5:0 usbaddr[5:0] usb0 indirect register address bits. these bits hold a 6-bit address used to indirectly access the usb0 core registers. table 20.2 lists the usb0 core registers and their indirect addresses. reads and writes to usb0dat will target the regi ster indicated by the usbaddr bits.
c8051f380/1/2/3/4/5/6/7 174 rev. 1.0 sfr address = 0x97; sfr page = all pages sfr definition 20.3. usb0dat: usb0 data bit76543210 name usb0dat[7:0] type r/w reset 00000000 bit name description write read 7:0 usb0dat[7:0] usb0 data bits. this sfr is used to indi- rectly read and write usb0 registers. write procedure: 1. poll for busy (usb0adr.7) => 0. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write data to usb0dat. 4. repeat (step 2 may be skipped when writing to the same usb0 register). read procedure: 1. poll for busy (usb0adr.7) => 0. 2. load the target usb0 register address into the usbaddr bits in register usb0adr. 3. write 1 to the busy bit in register usb0adr (steps 2 and 3 can be per- formed in the same write). 4. poll for busy (usb0adr.7) => 0. 5. read data from usb0dat. 6. repeat from step 2 (step 2 may be skipped when reading the same usb0 register; step 3 may be skipped when the autord bit (usb0adr.6) is logic 1).
rev. 1.0 175 c8051f380/1/2/3/4/5/6/7 table 20.2. usb0 controller registers usb register name usb register address description page number interrupt registers in1int 0x02 endpoint0 and endpoints1-3 in interrupt flags 184 out1int 0x04 endpoints1-3 out interrupt flags 185 cmint 0x06 common usb interrupt flags 186 in1ie 0x07 endpoint0 and endpoints1-3 in interrupt enables 187 out1ie 0x09 endpoints1-3 out interrupt enables 188 cmie 0x0b common usb in terrupt enables 189 common registers faddr 0x00 function address 180 power 0x01 power management 182 framel 0x0c frame number low byte 183 frameh 0x0d frame number high byte 183 index 0x0e endpoint index selection 176 clkrec 0x0f clock recovery control 177 eenable 0x1e endpoint enable 194 fifon 0x20-0x23 endpoints0-3 fifos 179 indexed registers e0csr 0x11 endpoint0 control / status 192 eincsrl endpoint in control / status low byte 196 eincsrh 0x12 endpoint in control / status high byte 197 eoutcsrl 0x14 endpoint out control / status low byte 199 eoutcsrh 0x15 endpoint out control / status high byte 200 e0cnt 0x16 number of received bytes in endpoint0 fifo 193 eoutcntl endpoint out packet count low byte 200 eoutcnth 0x17 endpoint out packet count high byte 201
c8051f380/1/2/3/4/5/6/7 176 rev. 1.0 usb register address = 0x0e 20.4. usb clock configuration usb0 is capable of communication as a full or low speed usb function. communication speed is selected via the speed bit in sfr usb0xcn. when operati ng as a low speed func tion, the usb0 clock must be 6 mhz. when operating as a full speed functi on, the usb0 clock must be 48 mhz. clock options are described in section ?1 8. oscillators and clock sele ction? on page 139. the u sb0 clock is selected via sfr clksel (see sfr definition 18.1). clock recovery circuitry us es the incoming usb data stream to adju st the internal osc illator; this allows the internal oscillator to me et the requirements for usb clock tolera nce. clock recovery should be used in the following configurations: when operating usb0 as a low speed function with clock recovery, software must write 1 to the crlow bit to enable low speed clock recovery. clock recovery is typically not necessary in low speed mode. single step mode can be used to help the clock recovery circuitry to lock when high noise levels are pres- ent on the usb network. this mode is not requir ed (or recommended) in typical usb environments. usb register definition 20.4. i ndex: usb0 endpoint index bit76543210 name epsel[3:0] type rrrr r/w reset 00000000 bit name function 7:4 unused read = 0000b. write = don?t care. 3:0 epsel[3:0] endpoint select bits. these bits select which endpoint is targeted when indexed usb0 registers are accessed. 0000: endpoint 0 0001: endpoint 1 0010: endpoint 2 0011: endpoint 3 0100-1111: reserved. communication speed usb clock full speed internal oscillator low speed interna l oscillator / 8
rev. 1.0 177 c8051f380/1/2/3/4/5/6/7 usb register address = 0x0f usb register definition 20.5. cl krec: clock recovery control bit76543210 name cre crssen crlow type r/w r/w r/w r/w reset 00001111 bit name function 7 cre clock recovery enable bit. this bit enables/disables the usb clock recovery feature. 0: clock recovery disabled. 1: clock recovery enabled. 6 crssen clock recovery single step. this bit forces the oscillator calibration into single-step mode during clock recovery. 0: normal calibration mode. 1: single step mode. 5crlow low speed clock recovery mode. this bit must be set to 1 if clock recovery is used when operating as a low speed usb device. 0: full speed mode. 1: low speed mode. 4:0 reserved must write = 01111b.
c8051f380/1/2/3/4/5/6/7 178 rev. 1.0 20.5. fifo management 1024 bytes of on-chip xram are used as fifo sp ace for usb0. this fifo space is split between endpoints0-3 as shown in figure 20.3. fifo space allo cated for endpoints1-3 is configurable as in, out, or both (split mode: half in, half out). figure 20.3. usb fifo allocation 20.5.1. fifo split mode the fifo space for endpoints1-3 can be split such that the upper half of the fifo space is used by the in endpoint, and the lower half is used by the out endpo int. for example: if the endpoint3 fifo is config- ured for split mode, the upper 256 bytes (0x0540 to 0x063f) are used by endpoint3 in and the lower 256 bytes (0x0440 to 0x053f) are used by endpoint3 out. if an endpoint fifo is not configured for split mode, that endpoint in/out pair?s fifos are combined to form a single in or out fifo. in this case only one direction of the endpoint in/out pair may be used at a time. the endpoint direction (in/out) is determined by the dirsel bit in the corresponding endpoint?s eincsrh register (see sfr definition 20.13). endpoint0 (64 bytes) configurable as in, out, or both (split mode) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff user xram (1024 bytes) 0x0000 0x03ff usb clock domain system clock domain endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes)
rev. 1.0 179 c8051f380/1/2/3/4/5/6/7 20.5.2. fifo double buffering fifo slots for endpoints1-3 can be configured for double-buffered mode. in this mode, the maximum packet size is halved and the fifo may contain tw o packets at a time. this mode is available for endpoints1-3. when an endpoint is configured for sp lit mode, double buffering may be enabled for the in endpoint and/or the out endpoint. when split mode is not enabled, double-buffering may be enabled for the entire endpoint fifo. see table 20.3 for a list of maximum packet sizes for each fifo configuration. 20.5.1. fifo access each endpoint fifo is accessed through a correspond ing fifon register. a read of an endpoint fifon register unloads one byte from the fifo; a write of an endpoint fifon register loads one byte into the end- point fifo. when an endpoint fifo is configured for split mode, a read of the endpoint fifon register unloads one byte from the out endpoint fifo; a write of the endpoint fifon register loads one byte into the in endpoint fifo. usb register address = 0x20-0x23 table 20.3. fifo configurations endpoint number split mode enabled? maximum in packet size (double buffer disabled / enabled) maximum out packet size (double buffer disabled / enabled) 0n/a 64 1 n 128 / 64 y 64 / 32 64 / 32 2 n 256 / 128 y 128 / 64 128 / 64 3 n 512 / 256 y 256 / 128 256 / 128 usb register definition 20.6. fifo n: usb0 endpoint fifo access bit76543210 name fifodata[7:0] type r/w reset 0000000 0 bit name function 7:0 fifodata[7:0] endpoint fifo access bits. usb addresses 0x20-0x23 provide access to the 4 pairs of endpoint fifos: 0x20: endpoint 0 0x21: endpoint 1 0x22: endpoint 2 0x23: endpoint 3 writing to the fifo address loads data into the in fifo for the corresponding endpoint. reading from the fifo address unloads data from the out fifo for the corresponding endpoint.
c8051f380/1/2/3/4/5/6/7 180 rev. 1.0 20.6. function addressing the faddr register holds the current usb0 function address. software should write the host-assigned 7- bit function address to the faddr register when received as part of a set_address command. a new address written to faddr will not take effect (usb0 will not respond to the new address) until the end of the current transfer (typic ally following the status phase of the set_address command transfer). the update bit (faddr.7) is set to 1 by hardware when software writes a new address to the faddr regis- ter. hardware clears the update bit when the new address takes effect as described above. usb register address = 0x00 20.7. function configuration and control the usb register power (usb register definition 20.8) is used to configure and control usb0 at the device level (enable/dis able, reset/suspend/resume handling, etc.). usb reset: the usbrst bit (power.3) is set to 1 by hardware when reset signaling is detected on the bus. upon this detection, the following occur: 1. the usb0 address is reset (faddr = 0x00). 2. endpoint fifos are flushed. 3. control/status registers are reset to 0x00 (e0csr, eincsrl, eincsrh, eoutcsrl, eoutcsrh). 4. usb register index is reset to 0x00. 5. all usb interrupts (excluding the suspend interrupt) are enabled and their corresponding flags cleared. 6. a usb reset interrupt is generated if enabled. writing a 1 to the usbrst bit will generate an asynchronous usb0 re set. all usb regi sters are reset to their default values following this asynchronous reset. suspend mode: with suspend detection enabled (susen = 1), usb0 will enter suspend mode when suspend signaling is detected on th e bus. an interrupt will be genera ted if enabled (susinte = 1). the usb register definition 20.7. faddr: usb0 function address bit76543210 name update faddr[6:0] type rr/w reset 00000000 bit name function 7update function address update bit. set to 1 when software writes the faddr regi ster. usb0 clears this bit to 0 when the new address takes effect. 0: the last address written to faddr is in effect. 1: the last address written to faddr is not yet in effect. 6:0 faddr[6:0] function address bits. holds the 7-bit function address for usb0. this address should be written by software when the set_address standard device re quest is received on endpoint0. the new address takes effect when the device request completes.
rev. 1.0 181 c8051f380/1/2/3/4/5/6/7 suspend interrupt service routine (isr) should perf orm application-specific co nfiguration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. see section ?18.3. programmable internal high-f requency (h-f) oscillator? on page 142 for more details on internal oscillator configuration, incl uding the suspend mode feature of the internal oscillator. usb0 exits suspend mode when any of the following occur: (1) resume signaling is detected or gener- ated, (2) reset signaling is detected, or (3) a device or usb reset occurs. if suspended, the internal oscil- lator will exit suspe nd mode upon any of th e above liste d events. resume signaling: usb0 will exit suspend mode if resume signaling is det ected on the bus. a resume interrupt will be gen erated upon dete ction if enabled (resinte = 1) . software may force a remote wakeup by writing 1 to the resume bit (power.2). when forcing a remote wakeup, software should write resume = 0 to end resume signaling 10-15 ms after the remote wakeup is initiated (resume = 1). iso update: when software writes 1 to the isoup bit (p ower.7), the iso update function is enabled. with iso update enabled, new packets written to an iso in endpoint will not be transmitted until a new start-of-frame (sof) is received. if the iso in endpoint receives an in token before a sof, usb0 will transmit a zero-length packet. when isoup = 1, iso update is enabled for all iso endpoints. usb enable: usb0 is disabled following a power-on-reset (por). usb0 is enabled by clearing the usbinh bit (power.4). once written to 0, the usbinh can only be set to 1 by one of the following: (1) a power-on-reset (por), or (2) an asynchronous usb0 reset generated by writing 1 to the usbrst bit (power.3). software should perform all usb0 configuration before enabling usb0. the configuration sequence should be performed as follows: 1. select and enable the usb clock source. 2. reset usb0 by writing usbrst= 1. 3. configure and enable the usb transceiver. 4. perform any usb0 function configuration (interrupts, suspend detect). 5. enable usb0 by writing usbinh = 0.
c8051f380/1/2/3/4/5/6/7 182 rev. 1.0 usb register address = 0x01 usb register definition 20.8. power: usb0 power bit76543210 name isoud usbinh usbrst resume susmd susen type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7isoud iso update bit. this bit affects all in isochronous endpoints. 0: when software writes inprdy = 1, usb0 will send the packet when the next in token is received. 1: when software writes inprdy = 1, usb0 will wait for a sof token before sending the packet. if an in token is re ceived before a sof token, u sb0 will send a zero-length data packet. 6:5 unused read = 00b. write = don?t care. 4 usbinh usb0 inhibit bit. this bit is set to 1 following a power-on reset (por) or an asynchronous usb0 reset. software should clear this bi t after all usb0 transceiver in itialization is complete. soft- ware cannot set this bit to 1. 0: usb0 enabled. 1: usb0 inhibited. all usb traffic is ignored. 3 usbrst reset detect. read: 0: reset signaling is not present. 1: reset signaling detected on the bus. write: writing 1 to this bit forces an asynchronous usb0 reset. 2 resume force resume. writing a 1 to this bit while in suspend mode (susmd = 1) forces usb0 to generate resume signaling on the bus (a remote wakeup event). software should write resume = 0 after 10 to 15 ms to end the resume signaling. an interrupt is generated, and hard- ware clears susmd, when software writes resume = 0. 1susmd suspend mode. set to 1 by hardware when usb0 enters susp end mode. cleared by hardware when soft- ware writes resume = 0 (following a remote wakeup) or reads the cmint register after detection of resume signaling on the bus. 0: usb0 not in suspend mode. 1: usb0 in suspend mode. 0 susen suspend detection enable. 0: suspend detection disa bled. usb0 will ignore su spend signaling on the bus. 1: suspend detection enabled. usb0 will enter suspend mode if it detects suspend sig- naling on the bus.
rev. 1.0 183 c8051f380/1/2/3/4/5/6/7 usb register address = 0x0c usb register address = 0x0d 20.8. interrupts the read-only usb0 interrupt flags are located in the usb registers shown in usb register definition 20.11 through usb register definition 20.13. the associated interrupt enable bits are located in the usb registers shown in usb register definition 20.14 through usb register definition 20.16. a usb0 interrupt is generated when any of the usb interrupt flag s is set to 1. the usb0 interrupt is enabled via the eie1 sfr (see section ?15. interrupts? on page 115). important note : reading a usb interrupt flag register re sets all flags in that register to 0. usb register definition 20.9. fr amel: usb0 frame number low bit76543210 name frmel[7:0] type r reset 00000000 bit name function 7:0 frmel[7:0] frame number low bits. this register contains bits 7-0 of the last received frame number. usb register definition 20.10. fr ameh: usb0 frame number high bit76543210 name frmeh[2:0] type rrrrr r reset 00000000 bit name function 7:3 unused read = 00000b. write = don?t care. 2:0 frmeh[2:0] frame number high bits. this register contains bits 10-8 of the last received frame number.
c8051f380/1/2/3/4/5/6/7 184 rev. 1.0 usb register address = 0x02 usb register definition 20.11. in1in t: usb0 in endpoint interrupt bit76543210 name in3 in2 in1 ep0 type rrrrrrrr reset 00000000 bit name function 7:4 unused read = 0000b. write = don?t care. 3in3 in endpoint 3 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 3 interrupt inactive. 1: in endpoint 3 interrupt active. 2in2 in endpoint 2 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 2 interrupt inactive. 1: in endpoint 2 interrupt active. 1in1 in endpoint 1 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: in endpoint 1 interrupt inactive. 1: in endpoint 1 interrupt active. 0 ep0 endpoint 0 interrupt-pending flag. this bit is cleared when software reads the in1int register. 0: endpoint 0 interrupt inactive. 1: endpoint 0 interrupt active.
rev. 1.0 185 c8051f380/1/2/3/4/5/6/7 usb register address = 0x04 usb register definition 20.12. out1in t: usb0 out endpoint interrupt bit76543210 name out3 out2 out1 type rrrrrrrr reset 00000000 bit name function 7:4 unused read = 0000b. write = don?t care. 3out3 out endpoint 3 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 3 interrupt inactive. 1: out endpoint 3 interrupt active. 2out2 out endpoint 2 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 2 interrupt inactive. 1: out endpoint 2 interrupt active. 1out1 out endpoint 1 interrupt-pending flag. this bit is cleared when softwa re reads the out1int register. 0: out endpoint 1 interrupt inactive. 1: out endpoint 1 interrupt active. 0 unused read = 0b. write = don?t care.
c8051f380/1/2/3/4/5/6/7 186 rev. 1.0 usb register address = 0x06 usb register definition 20.13. cmint: usb0 common interrupt bit76543210 name sof rstint rsuint susint type rrrrrrrr reset 00000000 bit name function 7:4 unused read = 0000b. write = don?t care. 3sof start of frame interrupt flag. set by hardware when a sof token is receiv ed. this interrupt event is synthesized by hardware: an interrup t will be generated wh en hardware expects to receive a sof event, even if the actual sof signal is missed or corrupted. this bit is cleared when software reads the cmint register. 0: sof interrupt inactive. 1: sof interrupt active. 2rstint reset interrupt-pending flag. set by hardware when reset signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: reset interrupt inactive. 1: reset interrupt active. 1rsuint resume interrupt-pending flag. set by hardware when resume signaling is detected on the bus while usb0 is in sus- pend mode. this bit is cleared when software reads the cmint register. 0: resume interrupt inactive. 1: resume interrupt active. 0susint suspend interrupt-pending flag. when suspend detection is enabled (bit susen in register power), this bit is set by hardware when suspend signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: suspend interrupt inactive. 1: suspend interrupt active.
rev. 1.0 187 c8051f380/1/2/3/4/5/6/7 usb register address = 0x07 usb register definition 20.14. in1ie: usb0 in endpoint interrupt enable bit76543210 name in3e in2e in1e ep0e type rrrrr/wr/wr/wr/w reset 00001111 bit name function 7:4 unused read = 0000b. write = don?t care. 3in3e in endpoint 3 interrupt enable. 0: in endpoint 3 interrupt disabled. 1: in endpoint 3 interrupt enabled. 2in2e in endpoint 2 interrupt enable. 0: in endpoint 2 interrupt disabled. 1: in endpoint 2 interrupt enabled. 1in1e in endpoint 1 interrupt enable. 0: in endpoint 1 interrupt disabled. 1: in endpoint 1 interrupt enabled. 0 ep0e endpoint 0 interrupt enable. 0: endpoint 0 interrupt disabled. 1: endpoint 0 interrupt enabled.
c8051f380/1/2/3/4/5/6/7 188 rev. 1.0 usb register address = 0x09 usb register definition 20.15. out1ie: usb0 out endpoint interrupt enable bit76543210 name out3e out2e out1e type rrrrr/wr/wr/wr reset 00001110 bit name function 7:4 unused read = 0000b. write = don?t care. 3out3e out endpoint 3 interrupt enable. 0: out endpoint 3 interrupt disabled. 1: out endpoint 3 interrupt enabled. 2out2e out endpoint 2 interrupt enable. 0: out endpoint 2 interrupt disabled. 1: out endpoint 2 interrupt enabled. 1out1e out endpoint 1 interrupt enable. 0: out endpoint 1 interrupt disabled. 1: out endpoint 1 interrupt enabled. 0 unused read = 0b. write = don?t care.
rev. 1.0 189 c8051f380/1/2/3/4/5/6/7 usb register address = 0x0b usb register definition 20.16. cmie : usb0 common interrupt enable bit76543210 name sofe rstinte rsuinte susinte type rrrrr/wr/wr/wr/w reset 00000110 bit name function 7:4 unused read = 0000b. write = don?t care. 3sofe start of frame interrupt enable. 0: sof interrupt disabled. 1: sof interrupt enabled. 2rstinte reset interrupt enable. 0: reset interrupt disabled. 1: reset interrupt enabled. 1rsuinte resume interrupt enable. 0: resume interrupt disabled. 1: resume interrupt enabled. 0susinte suspend interrupt enable. 0: suspend interrupt disabled. 1: suspend interrupt enabled.
c8051f380/1/2/3/4/5/6/7 190 rev. 1.0 20.9. the serial interface engine the serial interface engine (sie) performs all low level usb protocol tasks, interrupting the processor when data has successfully been trans mitted or received. when receivin g data, the sie w ill interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat- ically generated by the sie. when transmitting data, the sie will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. the sie will not interrupt the processor when corr upted/erroneous packets are received. 20.10. endpoint0 endpoint0 is managed through the usb register e0cs r (usb register definition 20.18). the index reg- ister must be loaded with 0x00 to access the e0csr register. an endpoint0 interrupt is generated when: 1. a data packet (out or setup) has been receiv ed and loaded into the endpoint0 fifo. the oprdy bit (e0csr.0) is set to 1 by hardware. 2. an in data packet has successfully been unloaded from the endpoint0 fifo and transmitted to the host; inprdy is rese t to 0 by hardware. 3. an in transaction is completed (this interrupt generated during the status stage of the transaction). 4. hardware sets the ststl bit (e0csr.2) after a c ontrol transaction ended due to a protocol violation. 5. hardware sets the suend bit (e0csr.4) because a control transfer ended before firmware sets the dataend bit (e0csr.3). the e0cnt register (usb register definition 20.11) holds the number of received data bytes in the endpoint0 fifo. hardware will automatically detect protocol errors and send a stal l condition in resp onse. firmware may force a stall condition to abort the current transfer. when a stall condition is generated, the ststl bit will be set to 1 and an interrupt generated. the following conditions will cause ha rdware to generate a stall condition: 1. the host sends an out token during a out data phase after the dataend bit has been set to 1. 2. the host sends an in token during an in data phase after the dataend bit has been set to 1. 3. the host sends a packet that exceeds the maximum packet size for endpoint0. 4. the host sends a non-zero length data1 packet during the status phase of an in transaction. firmware sets the sdstl bit (e0csr.5) to 1. 20.10.1. endpoint0 setup transactions all control transfers must begin with a setup packe t. setup packets are similar to out packets, con- taining an 8-byte data field sent by the host. an y setup packet containing a command field of anything other than 8 bytes will be automatica lly rejected by usb0. an endpoint 0 interrupt is ge nerated when the data from a setup packet is loaded into the endpoint0 fifo. software should unload the command from the endpoint0 fifo, decode the comma nd, perform any necessary tasks, and set the soprdy bit to indi- cate that it has serviced the out packet. 20.10.2. endpoint0 in transactions when a setup request is received that requires u sb0 to transmit data to the host, one or more in requests will be sent by the host. fo r the first in transaction, firmware should load an in packet into the endpoint0 fifo, and set the inprdy bit (e0csr.1). an interrupt will be generated when an in packet is transmitted successfully. note that no interrupt will be generated if an in request is rece ived before firm-
rev. 1.0 191 c8051f380/1/2/3/4/5/6/7 ware has loaded a packet into the endpoint0 fifo. if the requested data exceeds the maximum packet size for endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the last (residual) packet. if the requested data is an inte- ger multiple of the maximum packet size for endpoint 0, the last data packet should be a zero-length packet signaling the end of the transfer. firmware should set the dataend bit to 1 after loading into the endpoint0 fifo the last data packet for a transfer. upon reception of the first in token for a particular control transfer, endpoint0 is said to be in transmit mode. in this mode, only in tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to 1 if a setup or out token is receiv ed while endpoint0 is in transmit mode. endpoint0 will remain in transmit m ode until any of th e following occur: 1. usb0 receives an end point0 setup or out token. 2. firmware sends a packet less than the maximum endpoint0 packet size. 3. firmware sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to 1 when performing (2) and (3) above. the sie will transmit a nak in response to an in token if there is no packet ready in the in fifo (inprdy = 0). 20.10.3. endpoint0 out transactions when a setup request is received that requires the host to transmit data to usb0, one or more out requests will be sent by the host. when an out pa cket is successfully receiv ed by usb0, hardware will set the oprdy bit (e0csr.0) to 1 and generate an endpoint0 interrupt. following this interrupt, firmware should unload the out packet from the endpoint 0 fifo and set the soprdy bit (e0csr.6) to 1. if the amount of data required for the transfer exceeds the maximum packet size for endpoint0, the data will be split into multiple packets. if the requested data is an integer multiple of the maximum packet size for endpoint0 (as reported to the host), the host will send a zero-l ength data packet signaling the end of the transfer. upon reception of the first out token for a particular control transfer, endpoint0 is said to be in receive mode. in this mode, only out tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to 1 if a setup or in token is re ceived while endpoint0 is in receive mode. endpoint0 will remain in receive mode until: 1. the sie receives a setup or in token. 2. the host sends a packet less than the maximum endpoint0 packet size. 3. the host sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to 1 when the expected amount of data has been received. the sie will transmit a st all condition if the host sends an out packet after the dataend bit has been set by firmware. an inte rrupt will be generated with the stst l bit (e0csr.2) set to 1 after the stall is transmitted.
c8051f380/1/2/3/4/5/6/7 192 rev. 1.0 usb register address = 0x11 usb register definition 20.17. e0 csr: usb0 endpoint0 control bit76543210 name ssuend soprdy sdstl suend dataend ststl inprdy oprdy type r/w r/w r/w r r/w r/w r/w r reset 00000000 bit name description write read 7 ssuend serviced setup end bit. software should set this bit to 1 after servicing a setup end (bit suend) event. hardware clears the suend bit when software writes 1 to ssuend. this bit always reads 0. 6soprdy serviced oprdy bit. software should wr ite 1 to this bit after servicing a received endpoint0 packet. the oprdy bit will be cleared by a write of 1 to soprdy. this bit always reads 0. 5sdstl send stall bit. software can write 1 to this bit to terminate the current transfer (due to an error condi- tion, unexpected transfer request, etc.). hardware will clear th is bit to 0 when the stall handshake is transmitted. 4 suend setup end bit. hardware sets this read-only bit to 1 when a control transaction ends before software has written 1 to the dataend bit. hardware clears this bit when software writes 1 to ssuend. 3 dataend data end bit. software should write 1 to this bit: 1) when writing 1 to inprdy for the last outgoing data packet. 2) when writing 1 to inprdy for a zero-length data packet. 3) when writ- ing 1 to soprdy after servicing the last incoming data packet. this bit is automatically cleared by hardware. 2 ststl sent stall bit. hardware sets this bit to 1 after transmitti ng a stall handshake signal. this flag must be cleared by software. 1 inprdy in packet ready bit. software should write 1 to this bit after loading a data packet into the endpoint0 fifo for transmit. hardware clears this bit and generates an interrupt under either of the fol- lowing conditions: 1) the packet is transmitted. 2) the packet is overwritten by an incoming setup packet. 3) the packet is overwritten by an incoming out packet. 0 oprdy out packet ready bit. hardware sets this read-only bit and generates an interrupt when a data packet has been received. this bit is cleared only w hen software writes 1 to the soprdy bit.
rev. 1.0 193 c8051f380/1/2/3/4/5/6/7 usb register address = 0x16 20.11. configuring endpoints1-3 endpoints1-3 are configured and controlled through thei r own sets of the following control/status registers: in registers eincsrl and eincsrh, and out regi sters eoutcsrl and eoutcsrh. only one set of endpoint control/status registers is mapped into the usb register address space at a time, defined by the contents of the index register (usb register definition 20.4). endpoints1-3 can be configured as in, out, or both in/out (split mode) as described in section 20.5.1. the endpoint mode (split/normal) is selected via the split bit in register eincsrh. when split = 1, the corresponding endpoint fifo is split, and both in and out pipes are available. when split = 0, the corresponding endpoint function s as either in or out; the endpoint direction is selected by the dirsel bit in register eincsrh. endpoints1-3 can be disabled individually by the corresponding bits in the enable register. when an endpoint is disabled, it will not resp ond to bus traffic or stall the bus. all endpoints are enabled by default. usb register definition 20.18. e0 cnt: usb0 endpoint0 data count bit76543210 name e0cnt[6:0] type rr reset 00000000 bit name function 7 unused read = 0b. write = don?t care. 6:0 e0cnt[6:0] endpoint 0 data count. this 7-bit number indicates the number of received data bytes in the endpoint 0 fifo. this number is only valid while bit oprdy is a 1.
c8051f380/1/2/3/4/5/6/7 194 rev. 1.0 usb register address = 0x1e 20.12. controlling endpoints1-3 in endpoints1-3 in are managed via usb registers ei ncsrl and eincsrh. all in endpoints can be used for interrupt, bulk, or isochronous tr ansfers. isochronous (iso) mode is enabled by writing 1 to the iso bit in register eincsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1-3 in interrupt is generate d by any of the following conditions: 1. an in packet is successfully transferred to the host. 2. software writes 1 to the flush bit (eincs rl.3) when the target fifo is not empty. 3. hardware generates a stall condition. 20.12.1. endpoints1-3 in interrupt or bulk mode when the iso bit (eincsrh.6) = 0 the target endpoint operates in bulk or interrupt mode. once an end- point has been configured to operate in bulk/interrupt in mode (typically following an endpoint0 set_interface command), firmware should load an in packet into the endpoint in fifo and set the inprdy bit (eincsrl.0). upon reception of an in token, hardware will tran smit the data, clear the inprdy bit, and generate an interrupt. writing 1 to inprdy without writing any data to th e endpoint fifo will cause a zero-length packet to be transmitted upon reception of the next in token. usb register definition 20.19. ee nable: usb0 endpoint enable bit76543210 name een3 een2 een1 type rrrrr/wr/wr/wr/w reset 11111111 bit name function 7:4 unused read = 1111b. write = don?t care. 3 een3 endpoint 3 enable. this bit enables/disables endpoint 3. 0: endpoint 3 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 3 is enabled (normal). 2 een2 endpoint 2 enable. this bit enables/disables endpoint 2. 0: endpoint 2 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 2 is enabled (normal). 1 een1 endpoint 1 enable. this bit enables/disables endpoint 1. 0: endpoint 1 is disabled (no nack , ack, or stall on the usb network). 1: endpoint 1 is enabled (normal). 0 reserved must write 1b.
rev. 1.0 195 c8051f380/1/2/3/4/5/6/7 a bulk or interrupt pipe can be shut down (or halted) by writing 1 to the sdstl bit (eincsrl.4). while sdstl = 1, hardware will respond to all in requests with a stall condit ion. each time hardware gener- ates a stall condition, an inte rrupt will be generated and the stst l bit (eincsrl.5) set to 1. the ststl bit must be rese t to 0 by firmware. hardware will automatically reset inprdy to 0 when a packet slot is open in the endpo int fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time. in this case, ha rdware will reset inprdy to 0 immedi ately after firmware loads the first packet into the fifo and sets inprdy to 1. an interrup t will not be generated in th is case; an interrupt will only be generated when a data packet is transmitted. when firmware writes 1 to the fcdt bit (eincsrh.3), the data togg le for each in packet will be toggled continuously, regardless of the handshake received from the host. this feature is typically used by inter- rupt endpoints functioning as rate feedback communication for isochronous endpoints. when fcdt = 0, the data toggle bit will only be togg led when an ack is sent from the host in response to an in packet. 20.12.2. endpoints1-3 in isochronous mode when the iso bit (eincsrh.6) is set to 1, the target endpoint operates in isochronous (iso) mode. once an endpoint has been configured fo r iso in mode, the host will send one in token (d ata request) per frame; the location of data within each frame may vary. because of this, it is recommended that double buffering be enabled for iso in endpoints. hardware will automatically reset in prdy (eincsrl.0) to 0 when a packet slot is open in the endpoint fifo. note that if double buffering is enabled for the ta rget endpoint, it is possible for firmware to load two packets into the in fifo at a time . in this case, hardware will reset inprdy to 0 immediately after firm- ware loads the first packet into th e fifo and sets inprdy to 1. an interrupt will not be generated in this case; an interrupt will on ly be generated when a data packet is transmitted. if there is not a data packet ready in the endpoint fifo when usb0 receives an in token from the host, usb0 will transmit a zero-length data pack et and set the undrun bit (eincsrl.2) to 1. the iso update feature (see section 20.7) can be useful in starting a double buffered iso in endpoint. if the host has already set up the iso in pipe (has b egun transmitting in tokens) when firmware writes the first data packet to the endpoint fifo, the next in to ken may arrive and the first data packet sent before firmware has written the second (double buffered ) data packet to the fifo. the iso update feature ensures that any data packet written to the endpoint fifo will not be transmitte d during the current frame; the packet will only be sent after a sof signal has been received.
c8051f380/1/2/3/4/5/6/7 196 rev. 1.0 usb register address = 0x11 usb register definition 20.20. eincsrl: usb0 in endpoint control low bit76543210 name clrdt ststl sdstl flush undrun fifone inprdy type r w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description write read 7 unused read = 0b. write = don?t care. 6 clrdt clear data toggle bit. software should write 1 to this bit to reset the in end- point data toggle to 0. this bit always reads 0. 5ststl sent stall bit. hardware sets this bit to 1 when a stall handshake signal is transmitted. the fifo is flushed, and the inprdy bit cleared. this flag must be cleared by software. 4sdstl send stall. software should write 1 to this bit to generate a stall handshake in response to an in token. software should write 0 to this bit to terminate the stall signal. this bit has no effect in iso mode. 3flush fifo flush bit. writing a 1 to this bit flushes the next packe t to be transmitted from the in endpoint fifo. the fifo pointer is reset and the inprdy bit is cleared. if the fifo contains mul- tiple packets, software must write 1 to flush for each packet. hardware resets the flush bit to 0 when the fifo flush is complete. 2 undrun data underrun bit. the function of this bit depends on the in endpoint mode: iso: set when a zero-length packet is sent after an in token is received while bit inprdy = 0. interrupt/bulk: set when a nak is re turned in response to an in token. this bit must be cleared by software. 1fifone fifo not empty. 0: the in endpoint fifo is empty. 1. the in endpoint fifo contains one or more packets. 0 inprdy in packet ready. software should write 1 to this bit after load ing a data packet into the in endpoint fifo. hardware clears inprdy due to any of the following: 1) a data packet is transmitted. 2) double buffering is enabled (dbien = 1) and there is an open fifo packet slot. 3) if the endpoint is in isochronous mode (iso = 1) and isoud = 1, inprdy will read 0 until the next sof is received. note: an interrupt (if enabled) will be generated when hardware clears inprdy as a result of a packet being transmitted.
rev. 1.0 197 c8051f380/1/2/3/4/5/6/7 usb register address = 0x12 usb register definition 20.21. eincsrh: usb0 in endpoi nt control high bit76543210 name dbien iso dirsel fcdt split type r/w r/w r/w r r/w r/w r r reset 00000000 bit name function 7dbien in endpoint double-buffer enable. 0: double-buffering disabled for the selected in endpoint. 1: double-buffering enabled for the selected in endpoint. 6iso isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. 5 dirsel endpoint direction select. this bit is valid only when the sele cted fifo is not split (split = 0). 0: endpoint direction selected as out. 1: endpoint direction selected as in. 4 unused read = 0b. write = don?t care. 3fcdt force data toggle bit. 0: endpoint data toggle switches only when an ack is received following a data packet transmission. 1: endpoint data toggle forced to switch after every data packet is transmitted, regard- less of ack reception. 2 split fifo split enable. when split = 1, the selected endpoint fifo is split. the upper half of the selected fifo is used by the in endpoint; the lower half of the selected fifo is used by the out endpoint. 1:0 unused read = 00b. write = don?t care.
c8051f380/1/2/3/4/5/6/7 198 rev. 1.0 20.13. controlling endpoints1-3 out endpoints1-3 out are managed via usb registers eoutcsrl and eoutcsrh. all out endpoints can be used for interrupt, bulk, or isochronous transfers. isochronous (iso) mode is enabled by writing 1 to the iso bit in register eoutcsrh. bu lk and interrupt transfers are handled identically by hardware. an endpoint1-3 out interrupt may be generated by the following: 1. hardware sets the oprd y bit (eincsrl.0) to 1. 2. hardware generates a stall condition. 20.13.1. endpoints1-3 out interrupt or bulk mode when the iso bit (eoutcsrh.6) = 0 the target endpoi nt operates in bulk or interrupt mode. once an endpoint has been configured to operate in bulk/interrupt out mode (typically following an endpoint0 set_interface command), hardware will set the oprdy bit (eoutcsrl.0) to 1 and generate an interrupt upon reception of an out token and data packet. the number of bytes in the current out data packet (the packet ready to be unloaded from the fifo) is given in the eoutcnth and eoutcntl reg- isters. in response to this interrupt, firmware should unload the data packet from the out fifo and reset the oprdy bit to 0. a bulk or interrupt pipe can be shut down (or halt ed) by writing 1 to the sdstl bit (eoutcsrl.5). while sdstl = 1, hardware will res pond to all out requests with a stall condition. each ti me hardwar e gener- ates a stall condition, an interrupt will be generated and the ststl bit (eoutcsrl.6) set to 1. the ststl bit must be rese t to 0 by firmware. hardware will automatically set oprdy when a packet is ready in the out fifo. note that if double buff- ering is enabled for the target endpoint, it is possible for two packets to be ready in the out fifo at a time. in this case, hardware will se t oprdy to 1 immediately after firm ware unloads the first packet and resets oprdy to 0. a second interr upt will be generate d in this case. 20.13.2. endpoints1-3 out isochronous mode when the iso bit (eoutcsrh.6) is set to 1, the ta rget endpoint operates in isochronous (iso) mode. once an endpoint has been configured for iso out mode, the host will send exactly one data per usb frame; the location of the data packet within each frame may vary, however. because of this, it is recom- mended that double buffering be enabled for iso out endpoints. each time a data packet is received, hardware will l oad the received data packe t into the endpoint fifo, set the oprdy bit (eoutcsrl.0) to 1, and generate an interrupt (if enabled). firmware would typically use this interrupt to unload the data packet from the endpoint fifo and reset the oprdy bit to 0. if a data packet is received when there is no room in the endpoint fifo, an inte rrupt will be generated and the ovrun bit (eoutcsrl.2) set to 1. if usb0 receiv es an iso data packet with a crc error, the data packet will be loaded into the endpoint fifo, oprdy w ill be set to 1, an interrup t (if enabled) will be gen- erated, and the dataerr bit (eoutcsrl.3) will be set to 1. software shoul d check the dataerr bit each time a data packet is unloaded from an iso out endpoint fifo.
rev. 1.0 199 c8051f380/1/2/3/4/5/6/7 usb register address = 0x14 usb register definition 20.22. eoutcsrl: usb0 out endpoint control low byte bit76543210 name clrdt ststl sdstl flush daterr ovrun fifoful oprdy type w r/w r/w r/w r r/w r r/w reset 00000000 bit name description write read 7 clrdt clear data toggle bit. software should write 1 to this bit to reset the out end- point data toggle to 0. this bit always reads 0. 6ststl sent stall bit. hardware sets this bit to 1 when a stall ha ndshake signal is transmitted. this flag must be cleared by software. 5sdstl send stall bit. software should write 1 to this bit to generate a stall handshake. software should write 0 to this bit to terminate the stall signal. this bit has no effect in iso mode. 4flush fifo flush bit. writing a 1 to this bit flushes the next pa cket to be read from the out endpoint fifo. the fifo pointer is reset and the oprdy bit is cleared. multiple packets must be flushed individually. hardware resets the flush bit to 0 when the flush is complete. note: if data for the current packet has already been read from the fifo, the flush bit should not be used to flush the packet. instead, the fifo should be read manually. 3daterr data error bit. in iso mode, this bit is set by hardware if a received packet has a crc or bit-stuffing error. it is cleared when software clears oprdy. this bit is only valid in iso mode. 2 ovrun data overrun bit. this bit is set by hardware when an incoming data packet cannot be loaded into the out endpoint fifo. this bit is only valid in iso mode, and must be cleared by software. 0: no data overrun. 1: a data packet was lost because of a fu ll fifo since this flag was last cleared. 1fifoful out fifo full. this bit indicates the contents of the out fifo. if double buffering is enabled (dbien = 1), the fifo is full when the fifo contains tw o packets. if dbien = 0, the fifo is full when the fifo contains one packet. 0: out endpoint fifo is not full. 1: out endpoint fifo is full. 0oprdy out packet ready. hardware sets this bit to 1 and generates an interrupt when a data packet is available. software should clear this bit after each data packet is unloaded from the out endpoint fifo.
c8051f380/1/2/3/4/5/6/7 200 rev. 1.0 usb register address = 0x15 usb register address = 0x16 usb register definition 20.23. eoutcsrh : usb0 out endpoi nt control high byte bit76543210 name dboen iso type r/wr/wrrrrrr reset 00000000 bit name function 7dboen double-buffer enable. 0: double-buffering disabled for the selected out endpoint. 1: double-buffering enabled for the selected out endpoint. 6iso isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. 5:0 unused read = 000000b. write = don?t care. usb register definition 20.24. eoutcnt l: usb0 out endpoint count low bit76543210 name eocl[7:0] type r reset 00000000 bit name function 7:0 eocl[7:0] out endpoint count low byte. eocl holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. th is number is only valid while oprdy = 1.
rev. 1.0 201 c8051f380/1/2/3/4/5/6/7 usb register address = 0x17 usb register definition 20.25. eoutcnt h: usb0 out end point count high bit76543210 name eoch[1:0] type rrrrrrrr reset 00000000 bit name function 7:2 unused read = 000000b. write = don?t care. 1:0 eoch[1:0] out endpoint count high byte. eoch holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. th is number is only valid while oprdy = 1.
c8051f380/1/2/3/4/5/6/7 202 rev. 1.0 21. smbus0 and smbus1 (i 2 c compatible) the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. the c8051f380/1/2/3/4/5/6/7 devices contain tw o smbus interfaces, smbus0 and smbus1. reads and writes to the smbus by the system controlle r are byte oriented with the smbus interface auton- omously controlling the serial transfer of the data. data can be tr ansferred at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clo ck-low duration is available to accommodate devices with different speed capa bilities on the same bus. the smbus may operate as a master and/or slave, and may function on a bus with multiple masters. the smbus provides control of sda (serial data), scl (ser ial clock) generation and sy nchronization, arbitration logic, and start/stop control and generation. the smbus peripherals can be fully driven by software (i.e., software accepts/rejects slave addresses, and generates acks), or hardware slave address recogni- tion and automatic ack generation can be enabled to minimize software overhead. a block diagram of the smbus0 peripheral and the associated sfrs is show n in figure 21.1. smbus1 is identical,with the excep- tion of the available timer options for the clock sour ce, and the timer used to implement the scl low time- out feature. refer to the specific sfr definitions for more details. figure 21.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation
rev. 1.0 203 c8051f380/1/2/3/4/5/6/7 21.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following suppo rting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 21.2. smbus configuration figure 21.2 shows a typical smbus configuration. th e smbus specification allo ws any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc- tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on th e bus is limited only by th e requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 21.2. typical smbus configuration 21.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the ar bitration. it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledged (ack) with a low sda during a high scl (see figure 21.3). if the receiving device does not ack, the tran smitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl
c8051f380/1/2/3/4/5/6/7 204 rev. 1.0 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and direction bit. if the trans- action is a write operation from th e master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction an d free the bus. figure 21. 3 illustrates a typical smbus transaction. figure 21.3. smbus transaction 21.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is se nt by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 21.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?21.3.5. scl high (smbus free) timeout? on page 205). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while th e other transmits a low. since the bus is open-drain , the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 21.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extensio n is used during a transf er in order to allow slower slave devices to communicate with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 21.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. for the smbus0 interface, timer 3 is used to implement scl low timeouts. timer 4 is used on the smbus1 interface for scl low timeouts. the scl low timeout feature is enabled by setting the smbntoe bit in smbncf. the associated timer is forced to reload when scl is high, and allowed to count when scl is sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
rev. 1.0 205 c8051f380/1/2/3/4/5/6/7 low. with the associated timer enabled and configur ed to overflow after 25 ms (and smbntoe set), the timer interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 21.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the smbnfte bit in smbncf is set, th e bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the st art will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen- tation. 21.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is de termined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard- ware is acting as a data transmitter or receiver. when a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycl e so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 21.5 for more details on transmis- sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smbncn (smbus control register) to find the cause of the smbus interrupt. th e smbncn register is described in section 21.4.3; table 21.5 provides a quick smbncn decoding reference. 21.4.1. smbus conf iguration register the smbus configuration register (s mbncf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbu s timing and timeout options. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave in terrupts. when the inh bit is set, all slave events will be inhibited following the next start (interrupts will c ontinue for the duration of the current transfer).
c8051f380/1/2/3/4/5/6/7 206 rev. 1.0 the smbncs1?0 bits select the smbus clock source, wh ich is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 21.1.the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for exam- ple, timer 1 overflows may generate the smbus0 and smbus1 clock rates simultaneously. timer configu- ration is covered in section ?25. timers? on page 260. equation 21.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 21.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 21.2. equation 21.2. typical smbus bit rate figure 21.4 shows the typical scl generation described by equation 21.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will ne ver exceed the limits defined by equation equation 21.1. figure 21.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute minimum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 21.2 shows the min- table 21.1. smbus clock source selection smbncs1 smbncs0 smbus0 clock source smbus1 clock source 0 0 timer 0 overflow timer 0 overflow 0 1 timer 1 overflow timer 5 overflow 1 0 timer 2 high byte overflow timer 2 high byte overflow 1 1 timer 2 low byte overflow timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------- ------------------ ----------- - == bitrate f clocksourceoverflow 3 --------------- ----------------- ------------- - = scl timer source overflows scl high timeout t low t high
rev. 1.0 207 c8051f380/1/2/3/4/5/6/7 imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbntoe bit set, timer 3 (smbus0) and ti mer 5 (smbus1) should be configured to overflow after 25 ms in order to detect scl low timeouts (s ee section ?21.3.4. scl low timeout? on page 204). the smbus interfac e will force the associated timer to reload while scl is high, and allow the timer to count when scl is low. the timer interrupt service ro utine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by sett ing the smbnfte bit. when this bit is set, the bus will be considered free if sda and scl remain hi gh for more than 10 smbus clock source periods (see figure 21.4). 21.4.2. smbus timing control register the smbus timing control register (smbtc)is used to restrict the detection of a start condition under certain circumstances. in some sy stems where there is significant mis-match between the impedance or the capacitance on the sda and scl lines, it may be possible for scl to fall after sda during an address or data transfer. such an event can cause a false start detection on the bus. these kind of events are not expected in a standard smbus or i2c-compliant system. in most systems th is parameter should not be adjusted, and it is recommended that it be left at its default value. by default, if the scl falling edge is detected after th e falling edge of sda (i.e. one sysclk cycle or more), the device will detect this as a start condition. the smbtc re gister is used to increase the amount of hold time that is required between sda and scl falling before a star t is recognized. an addi- tional 2, 4, or 8 sysclks can be added to prevent false start detecti on in systems where the bus condi- tions warrant this. table 21.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
c8051f380/1/2/3/4/5/6/7 208 rev. 1.0 sfr address = 0xc1; sfr page = 0 sfr definition 21.1. smb0cf: smbus clock/configuration bit765 4 3210 name ensmb0 inh0 busy0 exthold0 smb 0toe smb0fte smb0cs[1:0] type r/w r/w r r/w r/w r/w r/w reset 000 0 0000 bit name function 7ensmb0 smbus0 enable. this bit enables the smbus0 interface when set to 1. when enabled, the interface constantly monitors the sda0 and scl0 pins. 6 inh0 smbus0 slave inhibit. when this bit is set to logic 1, the sm bus0 does not generate an interrupt when slave events occur. this effectively remo ves the smbus0 slave from the bus. mas- ter mode interrupts are not affected. 5 busy0 smbus0 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold0 smbus0 setup and hold time extension enable. this bit controls the sda0 setup and hold times according to table 21.2. 0: sda0 extended setup and hold times disabled. 1: sda0 extended setup and hold times enabled. 3smb0toe smbus0 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus0 forces timer 3 to reload while scl0 is high and allows timer 3 to count when scl0 goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl0 is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus0 communica- tion. 2smb0fte smbus0 free timeout detection enable. when this bit is set to logic 1, the bu s will be considered free if scl0 and sda0 remain high for more than 10 smbus clock source periods. 1:0 smb0cs[1:0] smbus0 clock source selection. these two bits select the smbus0 clock source, which is used to generate the smbus0 bit rate. the selected device should be configured according to equation 21.1. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow
rev. 1.0 209 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc1; sfr page = f sfr definition 21.2. smb1cf: smbus clock/configuration bit765 4 3210 name ensmb1 inh1 busy1 exthold1 smb 1toe smb1fte smb1cs[1:0] type r/w r/w r r/w r/w r/w r/w reset 000 0 0000 bit name function 7ensmb1 smbus1 enable. this bit enables the smbus1 interface when set to 1. when enabled, the interface constantly monitors the sda1 and scl1 pins. 6 inh1 smbus1 slave inhibit. when this bit is set to logic 1, the sm bus1 does not generate an interrupt when slave events occur. this effectively remo ves the smbus1 slave from the bus. mas- ter mode interrupts are not affected. 5 busy1 smbus1 busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold1 smbus1 setup and hold time extension enable. this bit controls the sda1 setup and hold times according to table 21.2. 0: sda1 extended setup and hold times disabled. 1: sda1 extended setup and hold times enabled. 3smb1toe smbus1 scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus1 forces timer 4 to reload while scl1 is high and allows timer 4 to count when scl1 goes low. if timer 4 is configured to split mode, only the high byte of the timer is held in reload while scl1 is high. timer 4 should be programmed to generate interrupts at 25 ms, and the timer 4 interrupt service routine should reset smbus1 communica- tion. 2smb1fte smbus1 free timeout detection enable. when this bit is set to logic 1, the bu s will be considered free if scl1 and sda1 remain high for more than 10 smbus clock source periods. 1:0 smb1cs[1:0] smbus1 clock source selection. these two bits select the smbus1 clock source, which is used to generate the smbus1 bit rate. the selected device should be configured according to equation 21.1. 00: timer 0 overflow 01: timer 5 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow
c8051f380/1/2/3/4/5/6/7 210 rev. 1.0 sfr address = 0xb9; sfr page = f sfr definition 21.3. smbtc: smbus timing control bit76543210 name smb1sdd[1:0] smb0sdd[1:0] type rrrr r/w r/w reset 00000000 bit name function 7:4 unused read = 0000b; write = don?t care. 3:2 smb1sdd[1:0] smbus1 start detection window these bits increase the hold time r equirement between sd a falling and scl fall- ing for start detection. 00: no additional hold ti me requirement (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 11: increase hold time window to 8-9 sysclks. 1:0 smb0sdd[1:0] smbus0 start detection window these bits increase the hold time r equirement between sd a falling and scl fall- ing for start detection. 00: no additional hold time window (0-1 sysclk). 01: increase hold time window to 2-3 sysclks. 10: increase hold time window to 4-5 sysclks. 11: increase hold time window to 8-9 sysclks.
rev. 1.0 211 c8051f380/1/2/3/4/5/6/7 21.4.3. smbncn control register smbncn is used to control the interface and to provid e status information (see sfr definition 21.4). the higher four bits of smbncn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop has been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause th e interface to generate a stop an d end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginnin g and end of each transfer, after each byte frame, or when an arbitration is lost; see table 21.3 for more details. important note about the si bit: the smbus interface is st alled while si is set; th us scl is held low, and the bus is stalled until software clears si. 21.4.3.1. software ack generation when the ehack bit in register smbn adm is cleared to 0, the firmware on the device must detect incom- ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ac krq is set each time a byte is re ceived, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if softwa re does not write the ack bit before clearing si. sda will reflect the defined ack va lue immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave ad dress is not acknowledged, further slave events will be ignored until the next start is detected. 21.4.3.2. hardwa re ack generation when the ehack bit in register sm b0adm is set to 1, automatic slav e address recognition and ack gen- eration is enabled. more detail about automatic slave address recognition can be found in section 21.4.4. as a receiver, the value currently sp ecified by the ack bit will be auto matically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored until the next start is detected, and no interr upt will be generated. table 21.3 lists all sources for hardware changes to the smbncn bits. refer to table 21.5 for smbus sta- tus decoding using the smbncn register.
c8051f380/1/2/3/4/5/6/7 212 rev. 1.0 sfr address = 0xc0; sfr pa ge = 0; bit-addressable sfr definition 21.4. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name master0 txmode0 sta0 sto0 ackrq0 arblost0 ack0 si0 type r r r/w r/w r r r/w r/w reset 00000 000 bit name description read write 7master0 smbus0 master/slave indicator. this read-only bit indicates when the smbus0 is operating as a master. 0: smbus0 operating in slave mode. 1: smbus0 operating in master mode. n/a 6 txmode0 smbus0 transmit mode indicator. this read-only bit indicates when the smbus0 is operating as a transmitter. 0: smbus0 in receiver mode. 1: smbus0 in transmitter mode. n/a 5sta0 smbus0 start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto0 smbus0 stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3 ackrq0 smbus0 acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost0 smbus0 arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack0 smbus0 acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si0 smbus0 interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si0 must be cleared by software. while si0 is set, scl0 is held low and the smbus0 is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and ini- tiate next state machine event. 1: force interrupt.
rev. 1.0 213 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc0; sfr page = f; bit-addressable sfr definition 21.5. smb1cn: smbus control bit 7 6 5 4 3 2 1 0 name master1 txmode1 sta1 sto1 ackrq1 arblost1 ack1 si1 type r r r/w r/w r r r/w r/w reset 00000 000 bit name description read write 7master1 smbus1 master/slave indicator. this read-only bit indicates when the smbus1 is operating as a master. 0: smbus1 operating in slave mode. 1: smbus1 operating in master mode. n/a 6 txmode1 smbus1 transmit mode indicator. this read-only bit indicates when the smbus1 is operating as a transmitter. 0: smbus1 in receiver mode. 1: smbus1 in transmitter mode. n/a 5sta1 smbus1 start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto1 smbus1 stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3 ackrq1 smbus1 acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost1 smbus1 arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack1 smbus1 acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si1 smbus1 interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si1 must be cleared by software. while si1 is set, scl1 is held low and the smbus1 is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and ini- tiate next state machine event. 1: force interrupt.
c8051f380/1/2/3/4/5/6/7 214 rev. 1.0 21.4.4. hardware slave address recognition the smbus hardware has th e capability to automatica lly recognize incoming sl ave addresses and send an ack without software intervention. automatic slave ad dress recognition is enabled by setting the ehack bit in register smb0adm to 1. th is will enable both automatic slav e address recognit ion and automatic hardware ack generation for received bytes (as a ma ster or slave). more detail on automatic hardware ack generation can be found in section 21.4.3.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register and the smbus slave address mask register. a single address or range of addresses (including the general call address 0x00) can be specif ied using these two regist ers. the most-significant seven bits of the two regist ers are used to define whic h addresses will be acked. a 1 in bit posi tions of the slave address mask slvm[6:0] enable a comparison between the received slave address and the hard- ware?s slave address slv[6:0] for th ose bits. a 0 in a bit of the slav e address mask means that bit will be treated as a ?don?t care? for comparison purposes. in this case, either a 1 or a 0 value are acceptable on table 21.3. sources for hardware changes to smbncn bit set by hardware when: cleared by hardware when: mastern ? a start is generated. ? a stop is generated. ? arbitration is lost. txmoden ? start is generated. ? smbndat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smbndat is not written before the start of an smbus frame. stan ? a start followed by an address byte is received. ? must be cleared by software. ston ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrqn ? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ? after each ack cycle. arblostn ? a repeated start is detected as a master when stan is low (unwanted repeated start). ? scln is sensed low while attempting to generate a stop or repeated start condition. ? sdan is sensed low wh ile transmitting a 1 (excluding ack bits). ? each time sin is cleared. ackn ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). sin ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software.
rev. 1.0 215 c8051f380/1/2/3/4/5/6/7 the incoming slave address. additionally, if the gcn bit in register smbnadr is se t to 1, hardware will rec- ognize the general call address (0x00). table 21.4 shows some example parameter settings and the slave addresses that will be recognized by hardware under those conditions. sfr address = 0xcf; sfr page = 0 table 21.4. hardware address recognition examples (ehack = 1) hardware slave address slvn[6:0] slave address mask slvmn[6:0] gcn bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c sfr definition 21.6. smb0adr: smbus0 slave address bit76543210 name slv0[6:0] gc0 type r/w r/w reset 00000000 bit name function 7:1 slv0[6:0] smbus hardware slave address. defines the smbus0 slave address(es) for automatic hardware acknowledge- ment. only address bits which have a 1 in the corresponding bit position in slvm0[6:0] are checked against the inco ming address. this allows multiple addresses to be recognized. 0gc0 general call address enable. when hardware address reco gnition is enabled (ehack0 = 1), this bit will deter- mine whether the general call address (0 x00) is also recognized by hardware. 0: general call address is ignored. 1: general call addr ess is recognized.
c8051f380/1/2/3/4/5/6/7 216 rev. 1.0 sfr address = 0xce; sfr page = 0 sfr address = 0xcf; sfr page = f sfr definition 21.7. smb0adm : smbus0 slave address mask bit76543210 name slvm0[6:0] ehack0 type r/w r/w reset 11111110 bit name function 7:1 slvm0[6:0] smbus0 slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm0[6:0] enables compari- sons with the corresponding bit in slv0[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack0 hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. sfr definition 21.8. smb1adr: smbus1 slave address bit76543210 name slv1[6:0] gc1 type r/w r/w reset 00000000 bit name function 7:1 slv1[6:0] smbus1 hardware slave address. defines the smbus1 slave address(es) for automatic hardware acknowledge- ment. only address bits which have a 1 in the corresponding bit position in slvm1[6:0] are checked against the inco ming address. this allows multiple addresses to be recognized. 0gc1 general call address enable. when hardware address reco gnition is enabled (ehack1 = 1), this bit will deter- mine whether the general call address (0 x00) is also recognized by hardware. 0: general call address is ignored. 1: general call addr ess is recognized.
rev. 1.0 217 c8051f380/1/2/3/4/5/6/7 sfr address = 0xce; sfr page = f sfr definition 21.9. smb1adm : smbus1 slave address mask bit76543210 name slvm1[6:0] ehack1 type r/w r/w reset 11111110 bit name function 7:1 slvm1[6:0] smbus1 slave address mask. defines which bits of register smb1adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm1[6:0] enables compari- sons with the corresponding bit in slv1[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack1 hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
c8051f380/1/2/3/4/5/6/7 218 rev. 1.0 21.4.5. data register the smbus data register smbndat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the da ta register when the sin flag is set. software should not attempt to access the smbndat register when the smbus is enabled and the sin flag is cleared to logic 0, as the interface may be in the process of sh ifting a byte of data into or out of the register. data in smbndat is always shifted out msb first. after a byte has been received, the first bit of received data is located at the msb of smbndat. while data is being shifted out, data on the bus is simultaneously being shifted in. smbndat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slave receiver is made with the correct data or address in smbndat. sfr address = 0xc2; sfr page = 0 sfr definition 21.10. smb0dat: smbus data bit76543210 name smb0dat[7:0] type r/w reset 00000000 bit name function 7:0 smb0dat[7:0] smbus0 data. the smb0dat register contains a byte of data to be transmitted on the smbus0 serial interface or a byte that has just been received on the smbus0 serial inter- face. the cpu can read from or write to this register whenever the si0 serial inter- rupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si0 flag is set. when the si 0 flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this regis- ter.
rev. 1.0 219 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc2; sfr page = f sfr definition 21.11. smb1dat: smbus data bit76543210 name smb1dat[7:0] type r/w reset 00000000 bit name function 7:0 smb1dat[7:0] smbus1 data. the smb1dat register contains a byte of data to be transmitted on the smbus1 serial interface or a byte that has just been received on the smbus1 serial inter- face. the cpu can read from or write to this register whenever the si1 serial inter- rupt flag (smb1cn.0) is set to logic 1. the serial data in the register remains stable as long as the si1 flag is set. when the si 1 flag is not set, the system may be in the process of shifting data in/out and the cpu should not attempt to access this regis- ter.
c8051f380/1/2/3/4/5/6/7 220 rev. 1.0 21.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. as a transmitter, interrupts occur after the ack, regardless of whether hardware ack generation is enabled or not. 21.5.1. write se quence (master) during a write sequence, an smbus mast er writes data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case th e data direction bit (r/w) will be logic 0 (write). the ma ster then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. the in terface will switch to master receiver mode if smb0dat is not written following a master transmitter interrupt. figure 21.5 shows a typical master write sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hard ware ack generation is enabled. figure 21.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 1.0 221 c8051f380/1/2/3/4/5/6/7 21.5.2. read sequence (master) during a read sequence, an smbus master reads data fr om a slave device. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must write the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writi ng a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the interface will switch to ma ster transmitter mode if smb0dat is written while an active master receiver. figure 21.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 21.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f380/1/2/3/4/5/6/7 222 rev. 1.0 21.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. if hardware ack gene ration is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, th e hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardwa re), slave interrupts w ill be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must write the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave receiver mode after receiving a stop. the in terface will switch to slave trans- mitter mode if smb0dat is written wh ile an active slave receiver. figure 21.7 shows a typical slave write sequence. two received data bytes are shown, thou gh any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at differ ent places in the sequence, depending on whether hard- ware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation dis- abled, and after the ack when hardware ack generation is enabled. figure 21.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
rev. 1.0 223 c8051f380/1/2/3/4/5/6/7 21.5.4. read se quence (slave) during a read sequence, an smbus master reads data fr om a slave device. the slave in this transfer will be a receiver during the address byte, and a transmitter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the in terrupt will occu r after the ack cycle. if the received slave address is ignore d (by software or hardwa re), slave interrupts w ill be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans- mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit- ted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknow ledge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be gen erated if smb0dat is wr itten following a received nack while in slave transmitter mode ). the interface exits slave transmitter mode after receiving a stop. the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 21.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 21.8. typical slave read sequence 21.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 21.5 descri bes the typical actions when hardware slave address recognition and ack generation is disabled. table 21. 6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ- ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi- cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f380/1/2/3/4/5/6/7 224 rev. 1.0 table 21.5. smbus status decoding: hardware ack disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indicate last byte, and send stop. 010 ? send nack to indicate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indicate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
rev. 1.0 225 c8051f380/1/2/3/4/5/6/7 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, acknowledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x lost arbitration as master; slave address + r/w received; ack requested. if write, acknowledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 11x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? table 21.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f380/1/2/3/4/5/6/7 226 rev. 1.0 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1 0 0 1110 table 21.6. smbus status decoding: ha rdware ack enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 table 21.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 1.0 227 c8051f380/1/2/3/4/5/6/7 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? table 21.6. smbus status decoding: hardwa re ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f380/1/2/3/4/5/6/7 228 rev. 1.0 slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 01x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 10x1110 table 21.6. smbus status decoding: hardwa re ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
rev. 1.0 229 c8051f380/1/2/3/4/5/6/7 22. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?22.1. enhanced baud rate generation? on page 230). received data buffering allows uart0 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the inte rrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 22.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set q d clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch)
c8051f380/1/2/3/4/5/6/7 230 rev. 1.0 22.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 22.2), which is not user- accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 22.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?25.1.3. mode 2: 8-bit coun- ter/timer with auto-reload? on page 264). the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate frequenc y. note that timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, th e external oscillator cl ock/8, or an external input t1. for any given timer 1 clock source, the ua rt0 baud rate is determined by equation 22.1-a and equation 22.1-b. equation 22.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?25. timers? on page 260. a quick ref- erence for typical baud rates and syst em clock frequencies is given in table 22.1. the internal oscillator may still generate the system clock when the external o scillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------ ------------- - = a) b)
rev. 1.0 231 c8051f380/1/2/3/4/5/6/7 22.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown in figure 22.3. figure 22.3. uart interconnect diagram 22.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when softwa re writes a data byte to the sbuf 0 register. the ti0 transmit inter- rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the stop-bit time). data recep- tion can begin any time after the ren0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over- run, the first received 8 bits are la tched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbu f0 and rb80 will not be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 22.4. 8-bit uart timing diagram or rs-232 c8051xxxx rs-232 level xltr tx rx c8051xxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
c8051f380/1/2/3/4/5/6/7 232 rev. 1.0 22.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these co nditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 fl ag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag w ill not be set to 1. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 22.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 1.0 233 c8051f380/1/2/3/4/5/6/7 22.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generat e an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the uart interrupt handl er, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addresse d slave resets its mce0 bit to ignore all transmis- sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 22.6. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f380/1/2/3/4/5/6/7 234 rev. 1.0 sfr address = 0x98; sfr page = all pages; bit-addressable sfr definition 22.1. scon0: serial port 0 control bit76543210 name s0mode - mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused read = 1b, write = don?t care. 5mce0 multiprocessor comm unication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is genera ted only when the ninth bit is logic 1. 4ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bit in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software.
rev. 1.0 235 c8051f380/1/2/3/4/5/6/7 sfr address = 0x99; sfr page = all pages sfr definition 22.2. sbuf0: seri al (uart0) port data buffer bit76543210 name sbuf0[7:0] type r/w reset 00000000 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch.
c8051f380/1/2/3/4/5/6/7 236 rev. 1.0 table 22.1. timer settings for standard baud rates using the internal oscillator target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor timer clock source sca1-sca0 (pre-scale select* t1m timer 1 reload value (hex) sysclk = 12 mhz 230400 230769 0.16% 52 sysclk xx 1 0xe6 115200 115385 0.16% 104 sysclk xx 1 0xcc 57600 57692 0.16% 208 sysclk xx 1 0x98 28800 28846 0.16% 416 sysclk xx 1 0x30 14400 14423 0.16% 832 sysclk / 4 01 0 0x98 9600 9615 0.16% 1248 sysclk / 4 01 0 0x64 2400 2404 0.16% 4992 sysclk / 12 00 0 0x30 1200 1202 0.16% 9984 sysclk / 48 10 0 0x98 sysclk = 24 mhz 230400 230769 0.16% 104 sysclk xx 1 0xcc 115200 115385 0.16% 208 sysclk xx 1 0x98 57600 57692 0.16% 416 sysclk xx 1 0x30 28800 28846 0.16% 832 sysclk / 4 01 0 0x98 14400 14423 0.16% 1664 sysclk / 4 01 0 0x30 9600 9615 0.16% 2496 sysclk / 12 00 0 0x98 2400 2404 0.16% 9984 sysclk / 48 10 0 0x98 1200 1202 0.16% 19968 sysclk / 48 10 0 0x30 sysclk = 48 mhz 230400 230769 0.16% 208 sysclk xx 1 0x98 115200 115385 0.16% 416 sysclk xx 1 0x30 57600 57692 0.16% 832 sysclk / 4 01 0 0x98 28800 28846 0.16% 1664 sysclk / 4 01 0 0x30 14400 14388 0.08% 3336 sysclk / 12 00 0 0x75 9600 9615 0.16% 4992 sysclk / 12 00 0 0x30 2400 2404 0.16% 19968 sysclk / 48 10 0 0x30 note: sca1-sca0 and t1m define the timer clock source. x = don?t care
rev. 1.0 237 c8051f380/1/2/3/4/5/6/7 23. uart1 uart1 is an asynchronous, full duplex serial port offeri ng a variety of data formatting options. a dedicated baud rate generator with a 16-bit timer and select able prescaler is included, which can generate a wide range of baud rates (details in section ?23.1. baud rate generator? on page 238). a received data fifo allows uart1 to receive up to three data bytes before data is lost and an overflow occurs. uart1 has six associated sfrs. three are used for the baud rate generator (sbcon1, sbrlh1, and sbrll1), two are used for data formatting, control, and status functions (scon1, smod1), and one is used to send and receive data (sbuf1). the single sbuf1 location provides access to both the transmit holding register and the receive fifo. writes to sbuf1 always access the transmit holding register. reads of sbuf1 always access the first byte of th e receive fifo; it is not possible to read data from the transmit holding register. with uart1 interrupts enabled, an interrupt is generated each time a transmit is completed (ti1 is set in scon1), or a data byte has been received (ri1 is set in scon1). the uart1 interrupt flags are not cleared by hardware when the cpu vectors to the inte rrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart1 interrupt (transmit complete or receive complete). note that if additional bytes are availabl e in the receive fifo, the ri1 bit cannot be cleared by software. figure 23.1. uart1 block diagram sbuf1 tx holding register rx fifo (3 deep) tx logic rx logic write to sbuf1 read of sbuf1 tx1 rx1 smod1 mce1 s1pt1 s1pt0 pe1 s1dl1 s1dl0 xbe1 sbl1 data formatting scon1 ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 control / status uart1 interrupt timer (16-bit) pre-scaler (1, 4, 12, 48) sysclk sbrlh1 sbrll1 overflow sbcon1 sb1run sb1ps1 sb1ps0 en baud rate generator
c8051f380/1/2/3/4/5/6/7 238 rev. 1.0 23.1. baud rate generator the uart1 baud rate is generated by a dedicated 16-bi t timer which runs from the controller?s core clock (sysclk), and has prescaler options of 1, 4, 12, or 48. the timer and prescaler options combined allow for a wide selection of baud rates over many sysclk frequencies. the baud rate generator is configured using th ree registers: sbcon1, sbrlh1, and sbrll1. the uart1 baud rate generator control register (sbcon1, sfr definition ) enables or disables the baud rate generator, and selects the prescaler value for the timer. the baud rate generator must be enabled for uart1 to function. registers sbrlh1 and sbrll1 contain a 16-bit reload value for the dedicated 16-bit timer. the internal timer counts up from the reload value on every clock tick. on timer overflows (0xffff to 0x0000), the timer is reloaded. for reliable uart operation, it is recommended that the uart baud rate is not configured for baud rate s faster than sysclk/1 6. the baud rate fo r uart1 is defined in equation 23.1. equation 23.1. uart1 baud rate a quick reference for typical baud rates and system clock frequencies is given in table 23.1. table 23.1. baud rate generator settings for standard baud rates target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor sb1ps[1:0] (prescaler bits) reload value in sbrlh1:sbrll1 sysclk = 12 mhz 230400 230769 0.16% 52 11 0xffe6 115200 115385 0.16% 104 11 0xffcc 57600 57692 0.16% 208 11 0xff98 28800 28846 0.16% 416 11 0xff30 14400 14388 0.08% 834 11 0xfe5f 9600 9600 0.0% 1250 11 0xfd8f 2400 2400 0.0% 5000 11 0xf63c 1200 1200 0.0% 10000 11 0xec78 sysclk = 24 mhz 230400 230769 0.16% 104 11 0xffcc 115200 115385 0.16% 208 11 0xff98 57600 57692 0.16% 416 11 0xff30 28800 28777 0.08% 834 11 0xfe5f 14400 14406 0.04% 1666 11 0xfcbf 9600 9600 0.0% 2500 11 0xfb1e 2400 2400 0.0% 10000 11 0xec78 1200 1200 0.0% 20000 11 0xd8f0 sysclk = 48 mhz 230400 230769 0.16% 208 11 0xff98 115200 115385 0.16% 416 11 0xff30 57600 57554 0.08% 834 11 0xfe5f 28800 28812 0.04% 1666 11 0xfcbf 14400 14397 0.02% 3334 11 0xf97d 9600 9600 0.0% 5000 11 0xf63c 2400 2400 0.0% 20000 11 0xd8f0 1200 1200 0.0% 40000 11 0xb1e0 baud rate sysclk 65536 (sbrlh1:sbrll1) ? ?? -------------------- --------------------- ------------------ ---------------- 1 2 -- - ? 1 prescaler ----------- ---------- - ? =
rev. 1.0 239 c8051f380/1/2/3/4/5/6/7 23.2. data format uart1 has a number of available options for data form atting. data transfers begin with a start bit (logic low), followed by the data bits (sent lsb-first), a parity or extra bit (if selected), and end with one or two stop bits (logic high). the data length is variable be tween 5 and 8 bits. a parity bit can be appended to the data, and automatically generated and detected by ha rdware for even, odd, mark, or space parity. the stop bit length is selectable between short (1 bit time) and long (1.5 or 2 bit times), and a multi-processor communication mode is available for implementing networked uart buses. all of the data formatting options can be configured using the smod1 register , shown in sfr definition . figure 23.2 shows the tim- ing for a uart1 transaction without parity or an extra bit enabled. figure 23.3 shows the timing for a uart1 transaction with parity enabled (pe1 = 1). fi gure 23.4 is an example of a uart1 transaction when the extra bit is enabled (xbe1 = 1). no te that the extra bit feature is no t available when parity is enabled, and the second stop bit is only an option for data lengths of 6, 7, or 8 bits. figure 23.2. uart1 timing without parity or extra bit figure 23.3. uart1 timing with parity figure 23.4. uart1 timing with extra bit d 1 d 0 d n-2 d n-1 start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 parity start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional d 1 d 0 d n-2 d n-1 extra start bit mark stop bit 1 bit times space n bits; n = 5, 6, 7, or 8 stop bit 2 optional
c8051f380/1/2/3/4/5/6/7 240 rev. 1.0 23.3. configurat ion and operation uart1 provides standard asynchronous, full duplex communication. it can operate in a point-to-point serial communications application, or as a node on a mult i-processor serial interface. to operate in a point- to-point application, where there are only two devices on the serial bus, the mce1 bit in smod1 should be cleared to 0. for o peration as part of a mult i-processor communications bu s, the mce1 and xbe1 bits should both be set to 1. in both types of applicatio ns, data is transmitted from the microcontroller on the tx1 pin, and received on the rx1 pin. the tx1 and rx1 pins are configured using the crossbar and the port i/o registers, as detailed in section ?19. port input/output? on page 150. in typical uart communications, the transmit (tx) ou tput of one device is conn ected to the receive (rx) input of the other device, either directly or th rough a bus transceiver, as shown in figure 23.5. figure 23.5. typical uart interconnect diagram 23.3.1. data transmission data transmission is double-buffered, and begins when software writes a data byte to the sbuf1 register. writing to sbuf1 places data in the transmit holdin g register, and the transmit holding register empty flag (thre1) will be cleared to 0. if the uarts shift register is empty (i.e. no transmission is in progress) the data will be placed in the shift register, and the th re1 bit will be set to 1. if a transmission is in prog- ress, the data will remain in the transmit holding register until the current transmission is complete. the ti1 transmit interrupt flag (scon1.1) will be set at t he end of any transmission (the beginning of the stop- bit time). if enabled, an interr upt will occur when ti1 is set. if the extra bit function is enabled (xbe1 = 1) and the parity function is disabled (pe1 = 0), the value of the tbx1 (scon1.3) bit will be sent in the extra bit position. when the pari ty function is enabled (pe1 = 1), hardware will generate the parity bit according to the selected parity type (s elected with s1pt[1:0]), and append it to the data field. note: when parity is enabled, the extra bit function is not available. 23.3.2. data reception data reception can begin any time after the ren1 receive enable bit (scon1.4) is set to logic 1. after the stop bit is received, the data byte w ill be stored in the receive fifo if the following conditions are met: the receive fifo (3 bytes deep) must not be full, and the stop bit(s) must be logic 1. in the event that the receive fifo is full, the incoming byte will be lost, and a receive fi fo overrun error will be generated (ovr1 in register scon1 will be set to logic 1). if the stop bit(s) were logic 0, the incoming data will not be stored in the receive fifo. if the reception conditions are met, the data is stored in the receive fifo, and the ri1 flag will be set. note: when mce1 = 1, ri1 will only be set if the extra bit was equal to 1. data can be read from the receive fifo by reading the sbuf1 register. the sbuf1 register represents the oldest byte in the fifo. after sbuf1 is read, the next byte in the fifo is immediately loaded into sbuf1, and space is made available in the fifo for another incomi ng byte. if enabled, an in terrupt will occur when ri1 is set. ri1 can only be cleared to '0' by software wh en there is no more inform ation in the fifo. the rec- ommended procedure to empty the fifo contents is: or rs-232 c8051fxxx rs-232 level translator tx rx c8051fxxx rx tx mcu rx tx pc com port
rev. 1.0 241 c8051f380/1/2/3/4/5/6/7 1. clear ri1 to 0 2. read sbuf1 3. check ri1, and repeat at step 1 if ri1 is set to 1. if the extra bit function is en abled (xbe1 = 1) and the parity function is disabled (pe1 = 0), the extra bit for the oldest byte in the fifo can be read from the rbx1 bit (scon1.2). if the extra bit function is not enabled, the value of the stop bit for the oldest fifo byte will be presen ted in rbx1. when the parity func- tion is enabled (pe1 = 1), hardwa re will check the receiv ed parity bit against the selected parity type (selected with s1pt[1:0]) wh en receiving data. if a byte with parity error is rece ived, the perr1 flag will be set to 1. this flag must be cleared by software. note: when parity is enabled, the extra bit function is not available. 23.3.3. mult iprocessor communications uart1 supports multiprocessor communication between a master processor and one or more slave pro- cessors by special use of the extra data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the tar get(s). an address byte differs from a data byte in that its extra bit is logic 1; in a data byte, the extra bit is always set to logic 0. setting the mce1 bit (smod1.7) of a slave processor configures its uart such that when a stop bit is received, the uart will generate an interrupt only if the extra bit is logic 1 (rbx1 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned address. if the addres ses match, the slave will clear its mce1 bit to enable interrupts on the reception of the following da ta byte(s). slaves that we ren't addressed leave their mce1 bits set and do not generate interrupts on the re ception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave resets its mce1 bit to ignore all trans- missions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 23.6. uart multi-processo r mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f380/1/2/3/4/5/6/7 242 rev. 1.0 sfr address = 0xd2; sfr page = all pages sfr definition 23.1. scon1: uart1 control bit76543210 name ovr1 perr1 thre1 ren1 tbx1 rbx1 ti1 ri1 type r/w r/w r r/w r/w r/w r/w r/w reset 00100000 bit name function 7ovr1 receive fifo overrun flag. this bit indicates a receive fifo overrun condition, where an incoming character is discarded due to a full fifo. this bit must be cleared to 0 by software. 0: receive fifo overrun has not occurred. 1: receive fifo overrun has occurred. 6 perr1 parity error flag. when parity is enabled, this bit indicates that a parity error has occurred. it is set to 1 when the parity of the oldest byte in the fifo does not match the selected parity type. this bit must be cleared to 0 by software. 0: parity error has not occurred. 1: parity error has occurred. 5 thre1 transmit holding register empty flag. 0: transmit holding register not empty - do not write to sbuf1. 1: transmit holding register empty - it is safe to write to sbuf1. 4ren1 receive enable. this bit enables/disables the uart receiver. when disabled, bytes can still be read from the receive fifo. 0: uart1 reception disabled. 1: uart1 reception enabled. 3 tbx1 extra transmission bit. the logic level of this bit will be assigned to the extra transmission bit when xbe1 = 1. this bit is not used when parity is enabled. 2 rbx1 extra receive bit. rbx1 is assigned the va lue of the extra bit when xbe1 = 1. if xbe1 is cleared to 0, rbx1 is assigned the logic level of the first stop bit. this bit is not valid when parity is enabled. 1ti1 transmit interrupt flag. set to a 1 by hardware after data has been transmitted at the beginning of the stop bit. when the uart1 interrupt is enabled, setting this bit c auses the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. 0ri1 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart1 (set at the stop bit sam- pling time). when the uart1 interrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. note that ri1 will remain set to '1' as long as there is still data in the uart fifo. after the last byte has been shifted from the fifo to sbuf1, ri1 can be cleared.
rev. 1.0 243 c8051f380/1/2/3/4/5/6/7 sfr address = 0xe5; sfr page = all pages sfr definition 23.2. smod1: uart1 mode bit76543210 name mce1 s1pt[1:0] pe1 s1dl[1:0] xbe1 sbl1 type r/w r/w r/w r/w r/w r/w reset 00001100 bit name function 7mce1 multiprocessor comm unication enable. 0: ri will be activated if stop bit(s) are 1. 1: ri will be activated if stop bit(s) and ex tra bit are 1 (extra bi t must be e nabled using xbe1). note: this function is not available when hardware parity is enabled. 6:5 s1pt[1:0] parity type bits. 00: odd 01: even 10: mark 11: space 4 pe1 parity enable. this bit activates hardware parity generation and checking. the parity type is selected by bits s1pt1-0 when parity is enabled. 0: hardware parity is disabled. 1: hardware parity is enabled. 3:2 s1dl[1:0] data length. 00: 5-bit data 01: 6-bit data 10: 7-bit data 11: 8-bit data 1 xbe1 extra bit enable. when enabled, the valu e of tbx1 will be app ended to the data field. 0: extra bit disabled. 1: extra bit enabled. 0sbl1 stop bit length. 0: short?stop bit is active for one bit time. 1: long?stop bit is active for two bit times (dat a length = 6, 7, or 8 bits), or 1.5 bit times (data length = 5 bits).
c8051f380/1/2/3/4/5/6/7 244 rev. 1.0 sfr address = 0xd3; sfr page = all pages sfr definition 23.3. sbuf1: uart1 data buffer bit76543210 name sbuf1[7:0] type r/w reset 00000000 bit name description write read 7:0 sbuf1[7:0] serial data buffer bits. this sfr is used to both send data from the uart and to read received data from the uart1 receive fifo. writing a byte to sbuf1 initiates the transmission. when data is written to sbuf1, it first goes to the transmit holding register, where it is held for serial transmission. when the transmit shift register is available, data is trans- ferred into the shift regis- ter, and sbuf1 may be written again. reading sbuf1 retrieves data from the receive fifo. when read, the old- est byte in the receive fifo is returned, and removed from the fifo. up to three bytes may be held in the fifo. if there are additional bytes avail- able in the fifo, the ri1 bit will remain at logic 1, even after being cleared by software.
rev. 1.0 245 c8051f380/1/2/3/4/5/6/7 sfr address = 0xac; sfr page = all pages sfr address = 0xb5; sfr page = all pages sfr definition 23.4. sbcon1: uart1 baud rate generator control bit76543210 name sb1run sb1ps[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved read = 0b. must write 0b. 6 sb1run baud rate generator enable. 0: baud rate generator is di sabled. uart1 will not function. 1: baud rate generator is enabled. 5:2 reserved read = 0000b. must write 0000b. 1:0 sb1ps[1:0] baud rate prescaler select. 00: prescaler = 12 01: prescaler = 4 10: prescaler = 48 11: prescaler = 1 sfr definition 23.5. sbrlh1: uart 1 baud rate generator high byte bit76543210 name sbrlh1[7:0] type r/w reset 00000000 bit name function 7:0 sbrlh1[7:0] uart1 baud rate reload high bits. high byte of reload value for uart1 baud rate generator.
c8051f380/1/2/3/4/5/6/7 246 rev. 1.0 sfr address = 0xb4; sfr page = all pages sfr definition 23.6. sbrll1: uart1 baud rate generator low byte bit76543210 name sbrll1[7:0] type r/w reset 00000000 bit name function 7:0 sbrll1[7:0] uart1 baud rate reload low bits. low byte of reload value fo r uart1 baud rate generator.
rev. 1.0 247 c8051f380/1/2/3/4/5/6/7 24. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) pr ovides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave devi ce in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slav e-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 24.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien
c8051f380/1/2/3/4/5/6/7 248 rev. 1.0 24.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 24.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 24.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance st ate when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not sele cted. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 24.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 24.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possible modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on th e bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 determ ines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 24.2, figure 24.3, and figure 24.4 for typica l connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?19. port input/output? on page 150 for general purpose port i/o and crossbar information. 24.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic
rev. 1.0 249 c8051f380/1/2/3/4/5/6/7 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb- first into the master's shift register. when a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another ma ster is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is gene rated (modf, spi0cn.5 = 1). mode fault w ill generate an interrupt if enabled. spi0 must be manually re-enabled in software under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 24.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 24.3 shows a connection diagram between a master devic e in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi 0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a sl ave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 24.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. figure 24.2. multiple-master mode connection diagram figure 24.3. 3-wire single master and 3-wire single slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck
c8051f380/1/2/3/4/5/6/7 250 rev. 1.0 figure 24.4. 4-wire single master mode and 4-wire slave mode connection diagram 24.3. spi0 slave mode operation when spi0 is enabled and not configured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. th e bit counter is reset on a falling ed ge of nss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 24.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0c n.3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 24.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 24.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will ge nerate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
rev. 1.0 251 c8051f380/1/2/3/4/5/6/7 ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be writte n.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 an d allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still ho lds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 24.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0c fg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0 cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 24.5. for slave mode, the clock and data relationships are shown in figure 24.6 and figure 24.7. note that ckpha should be set to 0 on both the master and slave spi w hen communicating be tween two silicon labs c8051 devices. the spi0 clock rate register (spi 0ckr) as shown in sfr definition 24.3 controls the master mode serial clock frequency. this register is ignored wh en operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial input data synchronously with the slave?s system clock.
c8051f380/1/2/3/4/5/6/7 252 rev. 1.0 figure 24.5. master mode data/clock timing figure 24.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0)
rev. 1.0 253 c8051f380/1/2/3/4/5/6/7 figure 24.7. slave mode data/clock timing (ckpha = 1) 24.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cf g configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
c8051f380/1/2/3/4/5/6/7 254 rev. 1.0 sfr address = 0xa1; sfr page = all pages sfr definition 24.1. spi0c fg: spi0 configuration bit7654321 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but rather a de-glitched ver- sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been tran sferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit w ill return to logic 0. rxbm t = 1 when in master mode. note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 24.1 for timing parameters.
rev. 1.0 255 c8051f380/1/2/3/4/5/6/7 sfr address = 0xf8; sfr page = all pages; bit-addressable sfr definition 24.2. spi0cn: spi0 control bit7654321 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0000011 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if spi interrupts are enabled, an interrupt will be ge nerated. this bit is not automatically cleared by hardware, and must be cleared by software. 6wcol write collision flag. this bit is set to logic 1 if a write to spi0dat is attempted when txbmt is 0. when this occurs, the write to spi0dat will be i gnored, and the transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5modf mode fault flag. this bit is set to logic 1 by hardware when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be gener ated. this bit is not automati cally cleared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi interrupts are enabled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 24.2 and section 24.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled.
c8051f380/1/2/3/4/5/6/7 256 rev. 1.0 sfr address = 0xa2; sfr page = all pages sfr address = 0xa3; sfr page = all pages sfr definition 24.3. spi0ckr: spi0 clock rate bit7654321 0 name scr[7:0] type r/w reset 0000000 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver- sion of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 m hz and spi0ckr = 0x04, sfr definition 24.4. spi0dat: spi0 data bit7654321 0 name spi0dat[7:0] type r/w reset 0000000 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- ---------------------- ----------------- - = f sck 2000000 241 + ?? ? --------------- ----------- = f sck 200 khz =
rev. 1.0 257 c8051f380/1/2/3/4/5/6/7 figure 24.8. spi master timing (ckpha = 0) figure 24.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
c8051f380/1/2/3/4/5/6/7 258 rev. 1.0 figure 24.10. spi slave timing (ckpha = 0) figure 24.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
rev. 1.0 259 c8051f380/1/2/3/4/5/6/7 table 24.1. spi slave timing parameters parameter description min max units master mode timing (see figure 24.8 and figure 24.9) t mckh sck high time 1 x t sysclk ?ns t mckl sck low time 1 x t sysclk ?ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 24.10 and figure 24.11) t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk).
c8051f380/1/2/3/4/5/6/7 260 rev. 1.0 25. timers each mcu includes six counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and four are 16-bit auto-reload timer for use with the smbus or for general purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical an d have four primary modes of operation. timer 2, 3, 4, and 5 offer 16-bit and split 8-bi t timer functionality with auto-reload. timers 0 and 1 may be clocked by one of five source s, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 25.1 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. timer 2, 3, 4, and 5 may be clocked by the system cl ock, the system clock divided by 12 , or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system clock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: timer 2, 3, 4, and 5 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
rev. 1.0 261 c8051f380/1/2/3/4/5/6/7 sfr address = 0x8e; sfr page = all pages sfr definition 25.1. ckcon: clock control bit76543210 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defi ned by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock)
c8051f380/1/2/3/4/5/6/7 262 rev. 1.0 sfr address = 0xe4; sfr page = f sfr definition 25.2. ckcon1: clock control 1 bit76543210 name t5mh t5ml t4mh t4ml type rrrrr/wr/wr/wr/w reset 00000000 bit name function 7:4 unused read = 0000b; write = don?t care 3t5mh timer 5 high byte clock select. selects the clock supplied to the timer 5 high byte (split 8-bit timer mode only). 0: timer 5 high byte uses the clock defined by the t5xclk bit in tmr5cn. 1: timer 5 high byte uses the system clock. 2t5ml timer 5 low byte clock select. selects the clock supplied to timer 5. selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 5 low byte uses the clock defined by the t5xclk bit in tmr5cn. 1: timer 5 low byte uses the system clock. 1t4mh timer 4 high byte clock select. selects the clock supplied to the timer 4 high byte (split 8-bit timer mode only). 0: timer 4 high byte uses the clock defined by the t4xclk bit in tmr4cn. 1: timer 4 high byte uses the system clock. 0t4ml timer 4 low byte clock select. selects the clock supplied to timer 4. if timer 4 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 4 low byte uses the clock defined by the t4xclk bit in tmr4cn. 1: timer 4 low byte uses the system clock.
rev. 1.0 263 c8051f380/1/2/3/4/5/6/7 25.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter; timer 1 interrupts can be enabled by setting the et1 bit in the ie register. both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 25.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit in the tmod register selects the counte r/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pi n (t0) increment the timer register (refer to section ?19.1. priority crossbar decoder? on page 151 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0 m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 25.1). setting the tr0 bit (tcon.4) enables the timer when eit her gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01cf. setting gate0 to 1 allows the timer to be controlled by the external input signal int0 , facilitating pulse width measurements setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf. tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care
c8051f380/1/2/3/4/5/6/7 264 rev. 1.0 figure 25.1. t0 mode 0 block diagram 25.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 25.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bi t counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer overflow fl ag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf 0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 in the tmod regi ster is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf (see sfr definition 15.7 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor t0m
rev. 1.0 265 c8051f380/1/2/3/4/5/6/7 figure 25.2. t0 mode 2 block diagram 25.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun- ter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is op erating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m
c8051f380/1/2/3/4/5/6/7 266 rev. 1.0 figure 25.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m
rev. 1.0 267 c8051f380/1/2/3/4/5/6/7 sfr address = 0x88; sfr page = all pages; bit-addressable sfr definition 25.3. tcon: timer control bit76543210 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2it1 interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 15.7). 0: int1 is level triggered. 1: int1 is edge triggered. 1ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 15.7). 0: int0 is level triggered. 1: int0 is edge triggered.
c8051f380/1/2/3/4/5/6/7 268 rev. 1.0 sfr address = 0x89; sfr page = all pages sfr definition 25.4. tmod: timer mode bit76543210 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 15.7). 6c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high -to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 15.7). 2c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high -to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
rev. 1.0 269 c8051f380/1/2/3/4/5/6/7 sfr address = 0x8a; sfr page = all pages sfr address = 0x8b; sfr page = all pages sfr definition 25.5. tl0: timer 0 low byte bit76543210 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 25.6. tl1: timer 1 low byte bit76543210 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
c8051f380/1/2/3/4/5/6/7 270 rev. 1.0 sfr address = 0x8c; sfr page = all pages sfr address = 0x8d; sfr page = all pages sfr definition 25.7. th0 : timer 0 high byte bit76543210 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 25.8. th1 : timer 1 high byte bit76543210 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
rev. 1.0 271 c8051f380/1/2/3/4/5/6/7 25.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, usb start-of-frame (sof) capture mode, or low-frequency os cillator (lfo) falling edge capture mode. the timer 2 operation mode is defined by the t2split (tmr2cn.3), t2ce (tmr2cn.4) bits, and t2css (tmr2cn.1) bits. timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 2 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized wi th the sys tem clock. 25.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16 -bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 25.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 25.4. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f380/1/2/3/4/5/6/7 272 rev. 1.0 25.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 25.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external clock select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.5. timer 2 8-bit mode block diagram 25.2.3. timer 2 capture modes: usb start-of-frame or lfo falling edge when t2ce = 1, timer 2 will operate in one of two special capture modes. the capture event can be selected between a usb start-of-frame (sof) capt ure, and a low-frequency oscillator (lfo) falling edge capture, using the t2css bit. the usb sof capture mode can be used to calibrate the system clock or external oscilla tor against the known usb host sof clo ck. the lfo falling-edg e capture mode can be used to calibrate th e internal low-freque ncy oscillator against the internal high-frequency oscillator or an external clock source. when t2split = 0, timer 2 counts up and overflows from 0xffff to 0x0000. t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.0 273 c8051f380/1/2/3/4/5/6/7 each time a capture event is received, the contents of the timer 2 registers (tmr2h:tmr2l) are latched into the timer 2 reload registers (tmr2rlh:tmr2rll). a timer 2 interrupt is generated if enabled. figure 25.6. timer 2 capture mode (t2split = 0) when t2split = 1, the timer 2 registers (tmr2h a nd tmr2l) act as two 8-bit counters. each counter counts up independently and overflows from 0xff to 0x00. each time a capture event is received, the con- tents of the timer 2 registers are latched into the timer 2 reload registers (tmr2rlh and tmr2rll). a timer 2 interrupt is generated if enabled. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh tclk 0 1 tr2 0 1 interrupt ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture usb start-of-frame (sof) enable tmr2cn t f 2 h t f 2 l t 2 x c l k t 2 c s s t r 2 t f 2 l e n t 2 c e t 2 s p l i t 0 1 t2css low-frequency oscillator falling edge to adc, smbus to smbus tl2 overflow
c8051f380/1/2/3/4/5/6/7 274 rev. 1.0 figure 25.7. timer 2 capture mode (t2split = 0) sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 1 0 tmr2h tmr2rlh tclk tmr2l tmr2rll to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2cn t f 2 h t f 2 l t 2 x c l k t 2 c s s t r 2 t f 2 l e n t 2 c e t 2 s p l i t capture enable capture interrupt usb start-of-frame (sof) low-frequency oscillator falling edge 0 1 t2css
rev. 1.0 275 c8051f380/1/2/3/4/5/6/7 sfr address = 0xc8; sfr pa ge = 0; bit-addressable sfr definition 25.9. tmr 2cn: timer 2 control bit76543210 name tf2h tf2l tf2len tf2cen t2split tr2 t2css t2xclk type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bi t causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 lo w byte interrupts. if ti mer 2 interrupts are also enabled, an in terrupt will be generat ed when the low byte of timer 2 overflows. 4tf2cen timer 2 low-frequency oscillator capture enable. when set to 1, this bit enables timer 2 low-frequency oscillator capture mode. if tf2cen is set and timer 2 interrupts are enabled, an interrupt will be generated on a falling edge of the low-fr equency oscillator output, an d the current 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2rll. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 2tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1t2css timer 2 capture source select. this bit selects the source of a capture event when bit t2ce is set to 1. 0: capture source is usb sof event. 1: capture source is falling edge of low-frequ ency oscillator. 0t2xclk timer 2 external clock select. this bit selects the external clock source for timer 2. however, the timer 2 clock select bits (t2mh and t2ml in register ck con) may still be used to select between the external clock and the syst em clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clock divided by 8 (synchronized with sysclk).
c8051f380/1/2/3/4/5/6/7 276 rev. 1.0 sfr address = 0xca; sfr page = 0 sfr address = 0xcb; sfr page = 0 sfr address = 0xcc; sfr page = 0 sfr definition 25.10. tmr2rll: ti mer 2 reload register low byte bit76543210 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 25.11. tmr2rlh: ti mer 2 reload register high byte bit76543210 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. sfr definition 25.12. tmr2l: timer 2 low byte bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value.
rev. 1.0 277 c8051f380/1/2/3/4/5/6/7 sfr address = 0xcd; sfr page = 0 sfr definition 25.13. tmr2h timer 2 high byte bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value.
c8051f380/1/2/3/4/5/6/7 278 rev. 1.0 25.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto-reload mode, usb start-of-frame (sof) capture mode, or low-frequency os cillator (lfo) rising ed ge capture mode. the ti mer 3 operation mode is defined by the t3split (tmr3cn.3), t3ce (tmr3cn.4) bits, and t3css (tmr3cn.1) bits. timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives the system clock while timer 3 (and/or the pca) is clocked by an external preci- sion oscillator. note that the external oscillator source divided by 8 is synchronized wi th the sys tem clock. 25.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded in to the timer 3 register as shown in figure 25.8, and the timer 3 high byte overflow fl ag (tmr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be gener ated on each timer 3 overflow. addition ally, if timer 3 in terrupts are enabled and the tf3len bit is set (tmr3cn. 5), an interr upt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 25.8. timer 3 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3css t3ce tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
rev. 1.0 279 c8051f380/1/2/3/4/5/6/7 25.3.2. 8-bit timers with auto-reload when t3split is 1 and t3ce = 0, timer 3 operates as two 8-bit timers (tmr3h and tmr3l). both 8-bit timers operate in auto-reload mode as shown in fi gure 25.9. tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3m h and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external clock select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over- flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.9. timer 3 8-bit mode block diagram 25.3.3. timer 3 capture modes: usb start-of-frame or lfo falling edge when t3ce = 1, timer 3 will operate in one of two special capture modes. the capture event can be selected between a usb start-of-frame (sof) capt ure, and a low-frequency oscillator (lfo) falling edge capture, using the t3css bit. the usb sof capture mode can be used to calibrate the system clock or external oscilla tor against the known usb host sof clo ck. the lfo falling-edg e capture mode can be used to calibrate th e internal low-freque ncy oscillator against the internal high-frequency oscillator or an external clock source. when t3split = 0, timer 3 counts up and overflows from 0xffff to 0x0000. each time a capture event is received, the contents of the timer 3 registers (tmr3h:tmr3l) are latched into the timer 3 reload registers (tmr3rlh:tmr3rll). a timer 3 interrupt is generated if enabled. t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3css t3ce tf3len tf3l tf3h t3xclk tr3 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m to adc
c8051f380/1/2/3/4/5/6/7 280 rev. 1.0 figure 25.10. timer 3 capture mode (t3split = 0) when t3split = 1, the timer 3 registers (tmr3h a nd tmr3l) act as two 8-bit counters. each counter counts up independently and overflows from 0xff to 0x00. each time a capture event is received, the con- tents of the timer 3 registers are latched into the timer 3 reload registers (tmr3rlh and tmr3rll). a timer 3 interrupt is generated if enabled. external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh tclk 0 1 tr3 0 1 interrupt to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture enable tmr3cn t f 3 h t f 3 l t 3 x c l k t 3 c s s t r 3 t f 3 l e n t 3 c e t 3 s p l i t usb start-of-frame (sof) 0 1 t3css low-frequency oscillator falling edge
rev. 1.0 281 c8051f380/1/2/3/4/5/6/7 figure 25.11. timer 3 capture mode (t3split = 0) sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 1 0 tmr3h tmr3rlh tclk tmr3l tmr3rll to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3cn t f 3 h t f 3 l t 3 x c l k t 3 c s s t r 3 t f 3 l e n t 3 c e t 3 s p l i t capture enable capture interrupt usb start-of-frame (sof) low-frequency oscillator falling edge 0 1 t3css
c8051f380/1/2/3/4/5/6/7 282 rev. 1.0 sfr address = 0x91; sfr page = 0 sfr definition 25.14. tm r3cn: timer 3 control bit76543210 name tf3h tf3l tf3len tf3cen t3split tr3 t3css t3xclk type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatica lly cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regard less of the timer 3 mode. this bit is not automatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 lo w byte interrupts. if ti mer 3 interrupts are also enabled, an in terrupt will be generat ed when the low byte of timer 3 overflows. 4tf3cen timer 3 low-frequency oscillator capture enable. when set to 1, this bit en ables timer 3 low-frequency oscillator capt ure mode. if tf3cen is set and timer 3 interrupts are enabled, an interrupt will be generated on a falling edge of the low-fr equency oscillator output, an d the current 16-bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3rll. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 2tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1t3css timer 3 capture source select. this bit selects the source of a capture event when bit t2ce is set to 1. 0: capture source is usb sof event. 1: capture source is falling edge of low-frequ ency oscillator. 0t3xclk timer 3 external clock select. this bit selects the external clock source for timer 3. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the syst em clock for either timer. 0: timer 3 clock is the system clock divided by 12. 1: timer 3 clock is the external clock divided by 8 (synchronized with sysclk).
rev. 1.0 283 c8051f380/1/2/3/4/5/6/7 sfr address = 0x92; sfr page = 0 sfr address = 0x93; sfr page = 0 sfr address = 0x94; sfr page = 0 sfr definition 25.15. tmr3rll: ti mer 3 reload register low byte bit76543210 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 25.16. tmr3rlh: ti mer 3 reload register high byte bit76543210 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3. sfr definition 25.17. tmr3l: timer 3 low byte bit76543210 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value.
c8051f380/1/2/3/4/5/6/7 284 rev. 1.0 sfr address = 0x95; sfr page = 0 sfr definition 25.18. tmr3h timer 3 high byte bit76543210 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value.
rev. 1.0 285 c8051f380/1/2/3/4/5/6/7 25.4. timer 4 timer 4 is a 16-bit timer formed by two 8-bit sfrs: tmr4l (low byte) and tmr4h (high byte). timer 4 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t4split bit (tmr4cn.3) defines timer 4 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. note that the external oscilla tor source divided by 8 is synchronized with the system clock. 25.4.1. 16-bit time r with auto-reload when t4split (tmr4cn.3) is zero, timer 4 operates as a 16-bit timer with auto-reload. timer 4 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 4 reload registers (tmr4rlh and tmr4rll) is loaded in to the timer 4 register as shown in figure 25.12, and the timer 4 high byte overflow fl ag (tmr4cn.7) is set. if timer 4 interrupts are enabled (if eie1.7 is set), an interrupt will be gener ated on each timer 4 overflow. addition ally, if timer 4 in terrupts are enabled and the tf4len bit is set (tmr4cn. 5), an interr upt will be generated each time the lower 8 bits (tmr4l) overflow from 0xff to 0x00. figure 25.12. timer 4 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr4l tmr4h tmr4rll tmr4rlh reload tclk 0 1 tr4 tmr4cn t4split t4css t4ce tf4l tf4h t4xclk tr4 0 1 t4xclk interrupt tf4len to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h
c8051f380/1/2/3/4/5/6/7 286 rev. 1.0 25.4.2. 8-bit timers with auto-reload when t4split is 1 and t4ce = 0, timer 4 operates as two 8-bit timers (tmr4h and tmr4l). both 8-bit timers operate in auto-reload mode as shown in figure 25.13. tmr4rll holds the reload value for tmr4l; tmr4rlh holds the reload value for tmr4h. the tr4 bit in tmr4cn handles the run control for tmr4h. tmr4l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 4 clock select bits (t4mh and t4ml in ckcon1) select either sysclk or the clock defined by the timer 4 external clock select bit (t4xclk in tmr4cn), as follows: the tf4h bit is set when tmr4h overflows from 0xff to 0x00; the tf4l bit is set when tmr4l overflows from 0xff to 0x00. when timer 4 interrupts are enabled, an interrupt is generated each time tmr4h over- flows. if timer 4 interrupts are enabled and tf4len (tmr4cn.5) is set, an interrupt is generated each time either tmr4l or tmr4h overflows. when tf4le n is enabled, software must check the tf4h and tf4l flags to determine the source of the timer 4 interrupt. the tf4h and tf4l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.13. timer 4 8-bit mode block diagram t4mh t4xclk tmr4h clock source t4ml t4xclk tmr4l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr4 external clock / 8 sysclk / 12 0 1 t4xclk 1 0 tmr4h tmr4rlh reload reload tclk tmr4l tmr4rll interrupt tmr4cn t4split t4css t4ce tf4len tf4l tf4h t4xclk tr4 to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h
rev. 1.0 287 c8051f380/1/2/3/4/5/6/7 sfr address = 0x91; sfr page = f sfr definition 25.19. tm r4cn: timer 4 control bit76543210 name tf4h tf4l tf4len t4split tr4 t4xclk type r/w r/w r/w r r/w r/w r r/w reset 00000000 bit name function 7 tf4h timer 4 high byte overflow flag. set by hardware when the timer 4 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 4 overflows from 0x ffff to 0x0000. when the timer 4 interrupt is enabled, setting this bit causes the cpu to vector to the timer 4 interrupt service routine. this bit is not automatica lly cleared by hardware. 6 tf4l timer 4 low byte overflow flag. set by hardware when the timer 4 low byte overflows from 0xff to 0x00. tf4l will be set when the low byte overflows regard less of the timer 4 mode. this bit is not automatically cleared by hardware. 5 tf4len timer 4 low byte interrupt enable. when set to 1, this bit enables timer 4 lo w byte interrupts. if ti mer 4 interrupts are also enabled, an in terrupt will be generat ed when the low byte of timer 4 overflows. 4 unused read = 0b; write = don?t care. 3 t4split timer 4 split mode enable. when this bit is set, timer 4 operates as two 8-bit timers with auto-reload. 0: timer 4 operates in 16-bit auto-reload mode. 1: timer 4 operates as tw o 8-bit auto-reload timers. 2tr4 timer 4 run control. timer 4 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr4h only; tmr4l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care. 0t4xclk timer 4 external clock select. this bit selects the external clock source for timer 4. however, the timer 4 clock select bits (t4mh and t4ml in regist er ckcon1) may still be used to select between the external clock and th e system clock for either timer. 0: timer 4 clock is the system clock divided by 12. 1: timer 4 clock is the external clock divided by 8 (synchronized with sysclk).
c8051f380/1/2/3/4/5/6/7 288 rev. 1.0 sfr address = 0x92; sfr page = f sfr address = 0x93; sfr page = f sfr address = 0x94; sfr page = f sfr definition 25.20. tmr4rll: ti mer 4 reload register low byte bit76543210 name tmr4rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr4rll[7:0] timer 4 reload register low byte. tmr4rll holds the low byte of the reload value for timer 4. sfr definition 25.21. tmr4rlh: ti mer 4 reload register high byte bit76543210 name tmr4rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr4rlh[7:0] timer 4 reload register high byte. tmr4rlh holds the high byte of the reload value for timer 4. sfr definition 25.22. tmr4l: timer 4 low byte bit76543210 name tmr4l[7:0] type r/w reset 00000000 bit name function 7:0 tmr4l[7:0] timer 4 low byte. in 16-bit mode, the tmr4l register contains the low byte of the 16-bit timer 4. in 8-bit mode, tmr4l contains the 8-bit low byte timer value.
rev. 1.0 289 c8051f380/1/2/3/4/5/6/7 sfr address = 0x95; sfr page = f sfr definition 25.23. tmr4h timer 4 high byte bit76543210 name tmr4h[7:0] type r/w reset 00000000 bit name function 7:0 tmr4h[7:0] timer 4 high byte. in 16-bit mode, the tmr4h register contains the high byte of the 16-bit timer 4. in 8-bit mode, tmr4h contains the 8-bit high byte timer value.
c8051f380/1/2/3/4/5/6/7 290 rev. 1.0 25.5. timer 5 timer 5 is a 16-bit timer formed by two 8-bit sfrs: tmr5l (low byte) and tmr5h (high byte). timer 5 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t5split bit (tmr5cn.3) defines timer 5 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. note that the external oscilla tor source divided by 8 is synchronized with the system clock. 25.5.1. 16-bit time r with auto-reload when t5split (tmr5cn.3) is zero, timer 5 operates as a 16-bit timer with auto-reload. timer 5 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 5 reload registers (tmr5rlh and tmr5rll) is loaded in to the timer 5 register as shown in figure 25.14, and the timer 5 high byte overflow fl ag (tmr5cn.7) is set. if timer 5 interrupts are enabled (if eie1.7 is set), an interrupt will be gener ated on each timer 5 overflow. addition ally, if timer 5 in terrupts are enabled and the tf5len bit is set (tmr5cn. 5), an interr upt will be generated each time the lower 8 bits (tmr5l) overflow from 0xff to 0x00. figure 25.14. timer 5 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr5l tmr5h tmr5rll tmr5rlh reload tclk 0 1 tr5 tmr5cn t5split t5css t5ce tf5l tf5h t5xclk tr5 0 1 t5xclk interrupt tf5len to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h
rev. 1.0 291 c8051f380/1/2/3/4/5/6/7 25.5.2. 8-bit timers with auto-reload when t5split is 1 and t5ce = 0, timer 5 operates as two 8-bit timers (tmr5h and tmr5l). both 8-bit timers operate in auto-reload mode as shown in figure 25.15. tmr5rll holds the reload value for tmr5l; tmr5rlh holds the reload value for tmr5h. the tr5 bit in tmr5cn handles the run control for tmr5h. tmr5l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 5 clock select bits (t5mh and t5ml in ckcon1) select either sysclk or the clock defined by the timer 5 external clock select bit (t5xclk in tmr5cn), as follows: the tf5h bit is set when tmr5h overflows from 0xff to 0x00; the tf5l bit is set when tmr5l overflows from 0xff to 0x00. when timer 5 interrupts are enabled, an interrupt is generated each time tmr5h over- flows. if timer 5 interrupts are enabled and tf5len (tmr5cn.5) is set, an interrupt is generated each time either tmr5l or tmr5h overflows. when tf5le n is enabled, software must check the tf5h and tf5l flags to determine the source of the timer 5 interrupt. the tf5h and tf5l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.15. timer 5 8-bit mode block diagram t5mh t5xclk tmr5h clock source t5ml t5xclk tmr5l clock source 0 0 sysclk/12 0 0 sysclk/12 0 1 external clock/8 0 1 external clock/8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr5 external clock / 8 sysclk / 12 0 1 t5xclk 1 0 tmr5h tmr5rlh reload reload tclk tmr5l tmr5rll interrupt tmr5cn t5split t5css t5ce tf5len tf5l tf5h t5xclk tr5 to adc ckcon1 t 4 m l t 4 m h t 5 m l t 5 m h
c8051f380/1/2/3/4/5/6/7 292 rev. 1.0 sfr address = 0xc8; sfr page = f; bit-addressable sfr definition 25.24. tm r5cn: timer 5 control bit76543210 name tf5h tf5l tf5len t5split tr5 t5xclk type r/w r/w r/w r r/w r/w r r/w reset 00000000 bit name function 7 tf5h timer 5 high byte overflow flag. set by hardware when the timer 5 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 5 overflows from 0x ffff to 0x0000. when the timer 5 interrupt is enabled, setting this bit causes the cpu to vector to the timer 5 interrupt service routine. this bit is not automatica lly cleared by hardware. 6 tf5l timer 5 low byte overflow flag. set by hardware when the timer 5 low byte overflows from 0xff to 0x00. tf5l will be set when the low byte overflows regard less of the timer 5 mode. this bit is not automatically cleared by hardware. 5 tf5len timer 5 low byte interrupt enable. when set to 1, this bit enables timer 5 lo w byte interrupts. if ti mer 5 interrupts are also enabled, an in terrupt will be generat ed when the low byte of timer 5 overflows. 4 unused read = 0b; write = don?t care. 3 t5split timer 5 split mode enable. when this bit is set, timer 5 operates as two 8-bit timers with auto-reload. 0: timer 5 operates in 16-bit auto-reload mode. 1: timer 5 operates as tw o 8-bit auto-reload timers. 2tr5 timer 5 run control. timer 5 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr5h only; tmr5l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care. 0t5xclk timer 5 external clock select. this bit selects the external clock source for timer 5. however, the timer 5 clock select bits (t5mh and t5ml in regist er ckcon1) may still be used to select between the external clock and th e system clock for either timer. 0: timer 5 clock is the system clock divided by 12. 1: timer 5 clock is the external clock divided by 8 (synchronized with sysclk).
rev. 1.0 293 c8051f380/1/2/3/4/5/6/7 sfr address = 0xca; sfr page = f sfr address = 0xcb; sfr page = f sfr address = 0xcc; sfr page = f sfr definition 25.25. tmr5rll: ti mer 5 reload register low byte bit76543210 name tmr5rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr5rll[7:0] timer 5 reload register low byte. tmr5rll holds the low byte of the reload value for timer 5. sfr definition 25.26. tmr5rlh: ti mer 5 reload register high byte bit76543210 name tmr5rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr5rlh[7:0] timer 5 reload register high byte. tmr5rlh holds the high byte of the reload value for timer 5. sfr definition 25.27. tmr5l: timer 5 low byte bit76543210 name tmr5l[7:0] type r/w reset 00000000 bit name function 7:0 tmr5l[7:0] timer 5 low byte. in 16-bit mode, the tmr5l register contains the low byte of the 16-bit timer 5. in 8-bit mode, tmr5l contains the 8-bit low byte timer value.
c8051f380/1/2/3/4/5/6/7 294 rev. 1.0 sfr address = 0xcd; sfr page = f sfr definition 25.28. tmr5h timer 5 high byte bit76543210 name tmr5h[7:0] type r/w reset 00000000 bit name function 7:0 tmr5h[7:0] timer 5 high byte. in 16-bit mode, the tmr5h register contains the high byte of the 16-bit timer 5. in 8-bit mode, tmr5h contains the 8-bit high byte timer value.
rev. 1.0 295 c8051f380/1/2/3/4/5/6/7 26. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between six sources: system clo ck, system clock divided by four, system clock divided by twel ve, the external oscillator clock source divided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre- quency output, 8-bit pwm, or 16-bit pwm (each m ode is described in section ?26.3. capture/compare modules? on page 298). the ex ternal oscillator clock opti on is ideal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precision external oscillator while the internal oscillator drives the sys- tem clock. the pca is configured and controlled th rough the system controller's special function regis- ters. the pca block diagram is shown in figure 26.1 important note: the pca module 4 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 26.4 for details. figure 26.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 3 capture/compare module 4 / wdt cex3 cex4
c8051f380/1/2/3/4/5/6/7 296 rev. 1.0 26.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the low byte (lsb). reading pca0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accurate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 26.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. figure 26.2. pca counter/timer block diagram table 26.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8 * 11xreserved note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8
rev. 1.0 297 c8051f380/1/2/3/4/5/6/7 26.2. pca0 interrupt sources figure 26.3 shows a diagram of the pca interrupt tree. there are six independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter and the indi vidual flags for each pca channel (ccf0, ccf1, ccf2, ccf3, and ccf4), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pca0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. figure 26.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 4) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 1 pca module 3 (ccf2) eccf3 0 1 pca module 4 (ccf2) eccf4
c8051f380/1/2/3/4/5/6/7 298 rev. 1.0 26.3. capture/compare modules each module can be configured to operate independ ently in one of six operat ion modes: edge-triggered capture, software timer, high-speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special function registers (sfrs) associated with it in the cip-51 sys- tem controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 26.2 summarizes the bit settings in the pca0cpmn register used to select the pca capture/compare module?s operating mode. setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 26.2. pca0cpm bit settings for pca capture/compare modules operational mode pca0cpmn bit number76543210 capture triggered by positive edge on cexn x x 1 0 0 0 0 a capture triggered by negative edge on cexn x x 0 1 0 0 0 a capture triggered by any transition on cexn x x 1 1 0 0 0 a software timer xb00100a high speed output x b 0 0 1 1 0 a frequency output x b 0 0 0 1 1 a 8-bit pulse width modulator 0 b 0 0 c 0 1 a 16-bit pulse width modulator 1 b 0 0 c 0 1 a notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 4. c = when set, a match event will cause the ccfn flag for the associated channel to be set.
rev. 1.0 299 c8051f380/1/2/3/4/5/6/7 26.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun- ter/timer and load it into the corresponding module 's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an inte rrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capn n bits are set to logic 1, then the state of the port pin associated with cexn can be r ead directly to determine whether a rising-edge or fall- ing-edge caused the capture. figure 26.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt x 000x x
c8051f380/1/2/3/4/5/6/7 300 rev. 1.0 26.3.2. software timer (compare) mode in software timer mode, the pca counter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a matc h occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 26.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
rev. 1.0 301 c8051f380/1/2/3/4/5/6/7 26.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compar e flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if th e ccfn interrupt for that module is enabled. the ccfn bit is not auto- matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleared, the associat ed pin will retain its stat e, and not t oggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 26.6. pca high-speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt
c8051f380/1/2/3/4/5/6/7 302 rev. 1.0 26.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte hol ds the number of pca clocks to count before the output is toggled. the frequency of the s quare wave is then defined by equation 26.1. equation 26.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg- ister. note that the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 counter and the 16-bit capt ure/compare register for the channel are equal. figure 26.7. pca frequency output mode f cexn f pca 2 pca 0 cphn ? ------------------- --------------------- - = note : a value of 0x00 in the pca0cphn register is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 1.0 303 c8051f380/1/2/3/4/5/6/7 26.3.5. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the co unt value in pca0l overflows, the cexn output will be reset (see figu re 26.8). also, when th e counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. if the matn bit is set to 1, the ccfn flag for the module will be set each time an 8-bit comparat or match (rising edge) occu rs. the duty cycle for 8- bit pwm mode is given in equation 26.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 26.2. 8-bit pwm duty cycle using equation 26.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 26.8. pca 8-bit pwm mode diagram duty cycle 256 pca 0 cphn ? ?? 256 ------------------ ----------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf
c8051f380/1/2/3/4/5/6/7 304 rev. 1.0 26.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod- ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a varying duty cycle, new va lue writes should be synchronized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, matc h interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compare register wr ites. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overfl ow (falling edge). the duty cycle for 16-bit pwm mode is given by equation 26.3. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 26.3. 16-bit pwm duty cycle using equation 26.3, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 26.9. pca 16-bit pwm mode duty cycle 65536 pca 0 cpn ? ?? 65536 ------------------ ------------------ ---------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
rev. 1.0 305 c8051f380/1/2/3/4/5/6/7 26.4. watchdog timer mode a programmable watchdog timer (wdt) function is av ailable through the pca module 4. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph4) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, modu le 4 operates as a watchdog timer (wdt). the mod- ule 4 high byte is compared to the pca counter high byte; the module 4 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this re set, the wdt should be explicitly disabled (and option- ally re-configured and re-enabled if it is used in the system). 26.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) are frozen. ? pca idle control bit (cidl) is frozen. ? module 4 is forced into software timer mode. ? writes to the module 4 mode register (pca0cpm4) are disabled. while the wdt is enabled, wr ites to the cr bit will not change the pca c ounter state; the counter will run until the wdt is disabled. the pca counter run co ntrol bit (cr) will read zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph4 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wdt may be updated with a write of any value to pca0cph4. upon a pca0cph4 write, pca0h plus the offset held in pca0cpl4 is loaded into pca0cph4 (see figure 26.10). figure 26.10. pca module 4 with watchdog timer enabled pca0h enable pca0l overflow reset pca0cpl4 8-bit adder pca0cph4 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph4 8-bit comparator
c8051f380/1/2/3/4/5/6/7 306 rev. 1.0 the 8-bit offset held in pca0cph4 is compared to th e upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a re set. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of th e pca0l when the update is performed. the total off- set is then given (in pca clocks) by equation 26.4, wher e pca0l is the value of the pca0l register at the time of the update. equation 26.4. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph4 and pca0h. software may force a wdt reset by writing a 1 to the ccf4 flag (pca0cn.4) while the wdt is enabled. 26.4.2. watchdog timer usage to configure the wdt, perform the following tasks: 1. disable the wdt by writing a 0 to the wdte bit. 2. select the desired pca cl ock source (with the cps2 ? cps0 bits). 3. load pca0cpl4 with the de sired wdt update offset value. 4. configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). 5. enable the wdt by setting the wdte bit to 1. 6. reset the wdt timer by writing to pca0cph4. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog timer is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any reset. the pca0 c ounter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl4 defaults to 0x00. using equation 26.4, this results in a wdt timeout interval of 256 pca clock cycles, or 3072 sys tem clock cycles. table 26.3 lists some example time- out intervals for typical system clocks. offset 256 pca 0 cpl 4 ? ?? 256 pca 0 l ? ?? + =
rev. 1.0 307 c8051f380/1/2/3/4/5/6/7 table 26.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl4 timeout interval (ms) 48,000,000 255 16.4 48,000,000 128 8.3 48,000,000 32 2.1 12,000,000 255 65.5 12,000,000 128 33.0 12,000,000 32 8.4 1,500,000 2 255 524.3 1,500,000 2 128 264.2 1,500,000 2 32 67.6 32,768 255 24,000 32,768 128 12,094 32,768 32 3,094 notes: 1. assumes sysclk/12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. internal sysclk reset frequency = internal oscillator divided by 8.
c8051f380/1/2/3/4/5/6/7 308 rev. 1.0 26.5. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr address = 0xd8; sfr page = all pages; bit-addressable sfr definition 26.1. pca0cn: pca control bit76543210 name cf cr ccf4 ccf3 ccf2 ccf1 ccf0 type r/w r/w r r/w r/w r/w r/w r/w reset 00000000 bit name function 7cf pca counter/timer overflow flag. set by hardware when the pca counter/ timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5 unused read = 0b, write = don't care. 2 ccf4 pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf4 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf3 pca module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf3 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 2 ccf2 pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 1 ccf1 pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software. 0 ccf0 pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service rou- tine. this bit is not automatically cleared by hardware and must be cleared by software.
rev. 1.0 309 c8051f380/1/2/3/4/5/6/7 sfr address = 0xd9; sfr page = all pages sfr definition 26.2. pca0md: pca mode bit76543210 name cidl wdte wdlck cps[2:0] ecf type r/w r/w r/w r r/w r/w reset 01000000 bit name function 7cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6wdte watchdog timer enable. if this bit is set, pca module 4 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 4 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog timer e nable. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 11x: reserved 0ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled.
c8051f380/1/2/3/4/5/6/7 310 rev. 1.0 sfr addresses: 0xda (n = 0), 0xdb (n = 1), 0xdc (n = 2), 0xdd (n = 3), 0xde (n = 4) sfr pages: all pages (n = 0), all pages (n = 1), all pages (n = 2), all pages (n = 3), all pages (n = 4) sfr definition 26.3. pca0cpmn: pca capture/compare mode bit76543210 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8-bit pwm selected. 1: 16-bit pwm selected. 6ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the ccfn bit in pca0md register to be set to logic 1. 2togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper- ates in frequency output mode. 1pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm4 register cannot be modified, and module 4 acts as the watchdog timer. to change the contents of the pca0cpm4 register or the function of module 4, the watchdog timer must be disabled.
rev. 1.0 311 c8051f380/1/2/3/4/5/6/7 sfr address = 0xf9; sfr page = all pages sfr address = 0xfa; sfr page = all pages sfr definition 26.4. pca0l: pca counter/timer low byte bit76543210 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register cannot be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 26.5. pca0h: pca counter/timer high byte bit76543210 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will read the contents of a ?snapsh ot? register, whose contents are updated only when the contents of pca0l are read (see section 26.1). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled.
c8051f380/1/2/3/4/5/6/7 312 rev. 1.0 sfr addresses: 0xfb (n = 0), 0xe9 (n = 1) , 0xeb (n = 2), 0xed (n = 3), 0xfd (n = 4) sfr pages: all pages (n = 0), all pages (n = 1), all pages (n = 2), all pages (n = 3), all pages (n = 4) sfr addresses: 0xfc (n = 0), 0xea (n = 1), 0xec (n = 2), 0xee (n = 3), 0xfe (n = 4) sfr pages: all pages (n = 0), all pages (n = 1), all pages (n = 2), all pages (n = 3), all pages (n = 4) sfr definition 26.6. pca0cpln: pca capture module low byte bit76543210 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 26.7. pca0cphn: pca capture module high byte bit76543210 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. note: a write to this register will set the module?s ecomn bit to a 1.
rev. 1.0 313 c8051f380/1/2/3/4/5/6/7 27. c2 interface c8051f380/1/2/3/4/5/6/7 devices include an on-chip si licon labs 2-wire (c2) debug interface to allow flash programming and in-system debugging with the produ ction part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-direc tional c2 data signal (c2d) to transfer information between the device and a hos t system. see the c2 interface specification for details on the c2 protocol. 27.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter- face. all c2 registers are accessed through the c2 inte rface as described in the c2 interface specification. c2 register definition 27.1. c2add: c2 address bit76543210 name c2add[7:0] type r/w reset 00000000 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xad selects the c2 flash programming data register for data read/write instructions
c8051f380/1/2/3/4/5/6/7 314 rev. 1.0 c2 address: 0x00 c2 address: 0x01 c2 register definition 27. 2. deviceid: c2 device id bit76543210 name deviceid[7:0] type r/w reset 00101000 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x28 (c8051f380/1/2/3/4/5/6/7). c2 register definition 27. 3. revid: c2 revision id bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a.
rev. 1.0 315 c8051f380/1/2/3/4/5/6/7 c2 address: 0x02 c2 address: 0xad c2 register definition 27.4. fpct l: c2 flash programming control bit76543210 name fpctl[7:0] type r/w reset 00000000 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. c2 register definition 27.5. fp dat: c2 flash programming data bit76543210 name fpdat[7:0] type r/w reset 00000000 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
c8051f380/1/2/3/4/5/6/7 316 rev. 1.0 27.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface c an safely ?borrow? the c2ck (rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 27.1. figure 27.1. typical c2 pin sharing the configuration in figure 27.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx
rev. 1.0 317 c8051f380/1/2/3/4/5/6/7 d ocument c hange l ist revision 0.2 to revison 1.0 ? updated electrical characteristics tables with latest data: table 4.2, table 4.4, table 4.5, table 4.7, table 4.8, table 4.10, table 4.11 and table 4.12. ? changed bit reg01cn.5 to reserved in sfr definiti on 8.1 and updated corresponding descriptions in sections 16.9 and 18.3.1. ? updated figure 18.1 . oscillator options. ? changed sfr page in sfr definition 21.2. ? updated descriptions of xoscmd for capacitor and rc modes in sfr definition 18.6.
c8051f380/1/2/3/4/5/6/7 318 rev. 1.0 c ontact i nformation silicon laboratories inc. silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tplease visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories re serves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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